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An Efficient Reconfiguration Algorithm for Degradable VLSI/WSI Arrays
June 2000 (vol. 49 no. 6)
pp. 553-559

Abstract—This paper considers the problem of reconfiguring two-dimensional degradable VLSI/WSI arrays under the constraint of row and column rerouting. The goal of the reconfiguration problem is to derive a fault-free subarray $T$ from the defective host array such that the dimensions of $T$ are larger than some specified minimum. This problem has been shown to be NP-complete under various switching and routing constraints. However, we show that a special case of the reconfiguration problem is optimally solvable in linear time. Using this result, a new fast and efficient reconfiguration algorithm is proposed. Empirical study shows that the new algorithm indeed produces good results in terms of the percentages of harvest and degradation of VLSI/WSI arrays.

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Index Terms:
Degradable VLSI/WSI arrays, NP-completeness, greedy algorithm, efficient heuristic.
Citation:
Chor Ping Low, "An Efficient Reconfiguration Algorithm for Degradable VLSI/WSI Arrays," IEEE Transactions on Computers, vol. 49, no. 6, pp. 553-559, June 2000, doi:10.1109/12.862215
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