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Tadayoshi Horita, Itsuo Takanami, "FaultTolerant Processor Arrays Based on the 1$\frac{1}{2}$Track Switches with Flexible Spare Distributions," IEEE Transactions on Computers, vol. 49, no. 6, pp. 542552, June, 2000.  
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@article{ 10.1109/12.862214, author = {Tadayoshi Horita and Itsuo Takanami}, title = {FaultTolerant Processor Arrays Based on the 1$\frac{1}{2}$Track Switches with Flexible Spare Distributions}, journal ={IEEE Transactions on Computers}, volume = {49}, number = {6}, issn = {00189340}, year = {2000}, pages = {542552}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.862214}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  FaultTolerant Processor Arrays Based on the 1$\frac{1}{2}$Track Switches with Flexible Spare Distributions IS  6 SN  00189340 SP542 EP552 EPD  542552 A1  Tadayoshi Horita, A1  Itsuo Takanami, PY  2000 KW  The 1$\frac{1}{2}$track switch model KW  meshconnected processor arrays KW  reconfiguration KW  wafer scale integration KW  yield enhancement. VL  49 JA  IEEE Transactions on Computers ER   
Abstract—A meshconnected processor array consists of many similar processing elements (PEs) which can be executed in both parallel and pipeline processing. For the implementation of an array of large numbers of processors, some faulttolerant issues are necessary to enhance the (fabricationtime) yield and the (runtime) reliability. In this paper, we propose a faulttolerant reconfigurable processor array using singletrack switches like Kung et al.'s model in [1]. The reconfiguration process in our model is executed based on the concept of the “compensation path” like Kung et al.'s method, too. In our model, spare PEs are not necessarily put around the array, but are more flexibly put in the array by changing connections between spare PEs and nonspare PEs while retaining the connections among nonspare PEs in the same manner in Kung et al.'s model. The proposed model has such a desirable property that physical distances between logically adjacent PEs in the reconfigured array are within a constant, that is, independent of sizes of arrays. We show that the hardware overhead of the proposed model is a little greater than that of Kung et al.'s model, while the yield of the proposed model is much better than that of Kung et al.'s model.
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