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Issue No.06 - June (2000 vol.49)
pp: 542-552
ABSTRACT
<p><b>Abstract</b>—A mesh-connected processor array consists of many similar processing elements (PEs) which can be executed in both parallel and pipeline processing. For the implementation of an array of large numbers of processors, some fault-tolerant issues are necessary to enhance the (fabrication-time) yield and the (run-time) reliability. In this paper, we propose a fault-tolerant reconfigurable processor array using single-track switches like Kung et al.'s model in [<ref type="bib" rid="bibT05421">1</ref>]. The reconfiguration process in our model is executed based on the concept of the “compensation path” like Kung et al.'s method, too. In our model, spare PEs are not necessarily put around the array, but are more flexibly put in the array by changing connections between spare PEs and nonspare PEs while retaining the connections among nonspare PEs in the same manner in Kung et al.'s model. The proposed model has such a desirable property that physical distances between logically adjacent PEs in the reconfigured array are within a constant, that is, independent of sizes of arrays. We show that the hardware overhead of the proposed model is a little greater than that of Kung et al.'s model, while the yield of the proposed model is much better than that of Kung et al.'s model.</p>
INDEX TERMS
The 1$\frac{1}{2}$-track switch model, mesh-connected processor arrays, reconfiguration, wafer scale integration, yield enhancement.
CITATION
Tadayoshi Horita, Itsuo Takanami, "Fault-Tolerant Processor Arrays Based on the 1$\frac{1}{2}$-Track Switches with Flexible Spare Distributions", IEEE Transactions on Computers, vol.49, no. 6, pp. 542-552, June 2000, doi:10.1109/12.862214
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