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IEEE Transactions on Computers
June 2000 (vol. 49 no. 6)
ISSN: 0018-9340
Table of Contents
SPECIAL SECTION ON DEFECT TOLERANCE OF DIGITAL SYSTEMS
Guest Editors' Introduction
(Abstract)
Fabrizio Lombardi
Mariagiovanna Sami
pp. 529-531
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Incorporating Yield Enhancement into the Floorplanning Process
(Abstract)
Israel Koren
Zahava Koren
pp. 532-541
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Fault-Tolerant Processor Arrays Based on the 1$\frac{1}{2}$-Track Switches with Flexible Spare Distributions
(Abstract)
Tadayoshi Horita
Itsuo Takanami
pp. 542-552
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An Efficient Reconfiguration Algorithm for Degradable VLSI/WSI Arrays
(Abstract)
Chor Ping Low
pp. 553-559
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Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines
(Abstract)
Cecilia Metra
Michele Favalli
Bruno Riccò
pp. 560-574
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On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults
(Abstract)
C. Thibeault
pp. 575-587
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Fault-Tolerant Newton-Raphson and Goldschmidt Dividers Using Time Shared TMR
(Abstract)
W. Lynn Gallagher
Earl E. Swartzlander
pp. 588-595
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REGULAR PAPERS
Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits
(Abstract)
Irith Pomeranz
Sudhakar M. Reddy
pp. 596-607
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Continuous Learning Automata Solutions to the Capacity Assignment Problem
(Abstract)
B. John Oommen
T. Dale Roberts
pp. 608-620
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