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| Nobuo Tsuda, "Fault-Tolerant Processor Arrays Using Additional Bypass Linking Allocated by Graph-Node Coloring," IEEE Transactions on Computers, vol. 49, no. 5, pp. 431-442, May, 2000. | |||
| BibTex | x | ||
| @article{ 10.1109/12.859538, author = {Nobuo Tsuda}, title = {Fault-Tolerant Processor Arrays Using Additional Bypass Linking Allocated by Graph-Node Coloring}, journal ={IEEE Transactions on Computers}, volume = {49}, number = {5}, issn = {0018-9340}, year = {2000}, pages = {431-442}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.859538}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Fault-Tolerant Processor Arrays Using Additional Bypass Linking Allocated by Graph-Node Coloring IS - 5 SN - 0018-9340 SP431 EP442 EPD - 431-442 A1 - Nobuo Tsuda, PY - 2000 KW - Processor array KW - mesh KW - tree KW - fault tolerance KW - k-out-of-n redundancy KW - additional bypass linking KW - graph-node coloring KW - enhanced communication and broadcast. VL - 49 JA - IEEE Transactions on Computers ER - | |||
Abstract—An advanced spare-connection scheme for
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