This Article 
 Bibliographic References 
 Add to: 
On the Design of IEEE Compliant Floating Point Units
May 2000 (vol. 49 no. 5)
pp. 398-413

Abstract—Engineering design methodology recommends designing a system as follows: Start with an unambiguous specification, partition the system into blocks, specify the functionality of each block, design each block separately, and glue the blocks together. Verifying the correctness of an implementation then reduces to a local verification procedure. We apply this methodology for designing a provably correct IEEE rounding unit that can be used for various operations, such as addition and multiplication. First, we provide a mathematical and, hopefully, unambiguous definition of the IEEE Standard which specifies the functionality. We give explicit and concise rules for gluing the rounding unit with a floating-point adder and multiplier. We then present floating-point addition and multiplication algorithms that use the rounding unit. To the best of our knowledge, our design is the first publication that deals with detecting exceptions and trapped overflow and underflow exceptions as an integral part of the rounding unit in a floating point unit. Our abstraction level avoids bit-level representations and arguments to help clarify the functionality of the algorithm.

[1] J.T. Coonen, “Specification for a Proposed Standard for Floating Point Arithmetic,” Memorandum ERL M78/72, Univ. of California, Berkeley, 1978.
[2] G. Even, S.M. Mueller, and P.M. Seidel, “A Dual Mode IEEE Multiplier,” Proc. Second IEEE Int'l Conf. Innovative Systems in Silicon, pp. 282-289, 1997.
[3] D. Goldberg, “Computer Arithmetic,” Computer Architecture: A Quantitative Approach, J.L. Hennessy and D.A. Patterson, eds., Appendix A, Morgan Kaufmann, 1990.
[4] J.M. Feldman and C.T. Retter, Computer Architecture: a Designer's Text Based on a Generic RISC. McGraw-Hill, 1994.
[5] I. Koren, Computer Arithmetic Algorithms.Englewood Cliffs, N.J.: Prentice Hall, 1993.
[6] ANSI/IEEE Std. 754-1985, Binary Floating-Point Arithmetic, IEEE Press, Piscataway, N.J., 1985 (also called ISO/IEC 559).
[7] D. Matula, “Floating Point Representation,” manuscript, May 1996.
[8] S.M. Müller and W. Paul, “The Decomposition Theorem for IEEE Floating Point Rounding,” manuscript, available at:http://www.wjp.CS.Uni-SB.DE/~smuellerpubli.html .
[9] S.M. Müller and W. Paul, “Complexity and Correctness of Computer Architectures,” Springer, 2000.
[10] A. Omondi, Computer Arithmetic Systems: Algorithms, Architectures, and Implementation. Prentice Hall, 1994.
[11] N. Quach, N. Takagi, and M. Flynn, “On Fast IEEE Rounding,” Technical Report CSL-TR-91-459, Stanford Univ., Jan. 1991.
[12] M.R. Santoro, G. Bewick, and M.A. Horowitz, “Rounding Algorithms for IEEE Multipliers,” Proc. Ninth Symp. Computer Arithmetic, pp. 176-183, 1989.
[13] P.-M. Seidel and G. Even, How Many Logic Levels Does Floating-Point Addition Require? Proc. 1998 Int'l Conf. Computer Design (ICCD '98): VLSI, in Computers&Processors, pp. 142-149, Oct. 1998.
[14] U. Sparmann, “Strukturbasierte Testmethoden für arithmetische Schaltkreise,” PhD dissertation, Universität des Saarlandes, 1991.
[15] S. Waser and M.J. Flynn,Introduction to Arithmetic for Digital System Designers.New York: CBS College Publishing, 1982.
[16] R.K. Yu and G.B. Zyner, “167 MHz Radix-4 Floating Point Multiplier,” Proc. 12th Symp. Computer Arithmetic, vol. 12, pp. 149-154, 1995.

Index Terms:
IEEE 754 Standard, floating-point arithmetic, floating-point rounding, floating-point addition.
Guy Even, Wolfgang J. Paul, "On the Design of IEEE Compliant Floating Point Units," IEEE Transactions on Computers, vol. 49, no. 5, pp. 398-413, May 2000, doi:10.1109/12.859536
Usage of this product signifies your acceptance of the Terms of Use.