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A Hierarchical Test Generation Approach for Large Controllers
April 2000 (vol. 49 no. 4)
pp. 289-302

Abstract—A testing approach targeted at Hardware Description Language (HDL)-based specifications of complex control devices is proposed. For such architectures, gate-level test pattern generators require insertion of scan paths to enable the flat gate-level representations to be efficiently handled. In contrast, we present a testing methodology based on the hierarchical finite state machine model. Our approach allows the generation of compact test sets with very high stuck-at fault coverages, without any design-for-testability logic other than hardware reset. This method can be used any time the functional information is available together with the gate-level structural description. High fault coverages are achieved with smaller test lengths and execution times with respect to state-of-the-art gate-level test pattern generators.

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Index Terms:
Functional testing, automatic test pattern generation, hierarchical FSM, functional fault model, sequential circuits.
Franco Fummi, Donatella Sciuto, "A Hierarchical Test Generation Approach for Large Controllers," IEEE Transactions on Computers, vol. 49, no. 4, pp. 289-302, April 2000, doi:10.1109/12.844343
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