Issue No.03 - March (2000 vol.49)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.841131
<p><b>Abstract</b>—A path delay fault in a sequential circuit will affect circuit timing only if it can be activated during normal operation of the circuit. Since vector pairs that can be applied to the next-state logic of a nonscan sequential circuit are restricted by the available state transitions, some faults may be impossible to activate. Such faults are redundant and need not be tested. In this paper, we present a method of identifying redundant path delay faults in the next-state logic implemented in a two-level sum of products form and extend it to multilevel realizations. Experimental results on MCNC '91 benchmarks show that large fractions of faults in most of the MCNC '91 benchmarks are redundant.</p>
Path delay faults, functional sensitizability, testability, redundant faults, sequential circuits.
Ramesh C. Tekumalla, "On Redundant Path Delay Faults in Synchronous Sequential Circuits", IEEE Transactions on Computers, vol.49, no. 3, pp. 277-282, March 2000, doi:10.1109/12.841131