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A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits
March 2000 (vol. 49 no. 3)
pp. 267-276

Abstract—A testable EXOR-Sum-of-Products (ESOP) circuit realization and a simple, universal test set which detects all single stuck-at faults in the internal lines and the primary inputs/outputs of the realization are given. Since ESOP is the most general form of AND-EXOR representations, our realization and test set are more versatile than those described by other researchers for the restricted GRM, FPRM, and PPRM forms of AND-EXOR circuits. Our circuit realization requires only two extra inputs for controllability and one extra output for observability. The cardinality of our test set for an $n$ input circuit is ($n+6$). For Built-in Self-Test (BIST) applications, we show that our test set can be generated internally as easily as a pseudorandom pattern and that it provides 100 percent single stuck-at fault coverage. In addition, our test set requires a much shorter test cycle than a comparable pseudoexhaustive or pseudorandom test set.

[1] M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design. New York: IEEE Press, 1990.
[2] S.M. Reddy, “Easily Testable Realizations for Logic Functions,” IEEE Trans. Computers, vol. 21, no. 11, pp. 1,183-1,188, Nov. 1972.
[3] D.K. Pradhan, “Universal Test Sets for Multiple Fault Detection in AND-EXOR Arrays,” IEEE Trans. Computers, vol. 27, no. 2, pp. 181-187, Feb. 1978.
[4] H. Fujiwara, Logic Testing and Design for Testability. MIT Press, 1985.
[5] T. Sasao, Logic Synthesis and Optimization. Kluwer Academic, 1993.
[6] A. Sarabi and M.A. Perkowski, “Design for Testability Properties of AND-EXOR Networks,” Proc. Int'l Workshop Applications of the Reed-Muller Expansion in Circuit Design, pp. 418-424, Sept. 1993.
[7] T. Sasao, “Easy Testable Realizations for Generalized Reed-Muller Expressions,” IEEE Trans. Computers, vol. 46, no. 6, pp. 709-716, June 1997.
[8] W. Daehn and J. Mucha, “A Hardware Approach to Self-Testing of Large Programmable Logic Arrays,” IEEE Trans. Computers, vol. 30, no. 11, pp. 829-833, Nov. 1981.
[9] J.P. Hayes, “On Modifying Logic Networks to Improve Their Diagnosability,” IEEE Trans. Computers, vol. 23, no. 1, pp. 56-62, 1974.
[10] S.M. Reddy and S. Kundu, “Fault Detection and Design for Testability of CMOS Logic Circuits,” Testing and Diagnosis of VLSI and ULSI, F. Lombardi and M. Sami, eds., pp. 69-91. Boston: Kluwer Academic, 1988.
[11] J.M. Cortner, Digital Test Engineering. New York: John Wiley&Sons, 1987.
[12] K.K. Saluja and S.M. Reddy, “Fault Detecting Test Sets for Reed-Muller Canonic Networks,” IEEE Trans. Computers, vol. 24, no. 10, pp. 995-998, Oct. 1975.
[13] T. Damarla and M.G. Karpovsky, “Reed-Muller Spectral Techniques for Fault Detection,” IEEE Trans. Computers, vol. 38, pp. 788-797, 1989.
[14] H. Fujiwara, “On Closedness and Test Complexity of Logic Circuits,” IEEE Trans. Computers, vol. 30, no. 8, pp. 556-562, Aug. 1981.
[15] K.L. Kodandapani, “A Note on Easily Testable Realizations for Logic Functions,” IEEE Trans. Computers, vol. 23, pp. 332-333, 1974.
[16] R. Drechsler, H. Hengster, H. Schfer, J. Hartmann, and B. Becker, “Testability of 2-level AND/EXOR Circuits,” Proc. European Design and Test Conf., Mar. 1997.
[17] E.M. Sentovich, J.K. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P.R. Stephan, R.K. Brayton, and A. Sangiovanni-Vincentelli, “SIS: A System for Sequential Circuit Synthesis,” Technical Report UCB/ERL M92/41, Electronics Research Laboratory, Univ. of California, Berkeley, May 1992.
[18] N. Song and M. Perkowski, "Minimization of Exclusive Sum-of-Products Expressions for Multiple-Valued Input, Incompletely Specified Functions," IEEE Trans. CAD, vol. 15, no 4, 1996, pp. 385-395.
[19] B.J. Falkowski and M.A. Perkowski, “An Algorithm for the Generation of Disjoint Cubes for Completely and Incompletely Specified Boolean Functions,” Int'l J. Electronics, vol. 70, no. 3, pp. 533-538, 1991.
[20] LSI Logic Corp., LCA/LEA500K Array-Based Products Databook, fourth ed., May 1997.
[21] Z. Zhao, B. Pouya, and N.A. Touba, BETSY: Synthesizing Circuits for a Specified BIST Environment Proc. Int'l Test Conf., pp. 144-153, Oct. 1998.
[22] A. Slusarczyk, L. Jozwiak, and M.A. Perkowski, “Term Trees in Application to an Effective and Efficient ATPG for AND-EXOR and AND-OR Circuits,” Proc. Int'l Workshop Applications of the Reed-Muller Expansion in Circuit Design, Aug. 1999.
[23] L.T. Wang and E.J. McCluskey, “Circuits for Pseudoexhaustive Test Pattern Generation,” IEEE Trans. Computer-Aided Design, vol. 7, no. 10, pp. 1,068-1,080, Oct. 1988.
[24] P.H. Bardell, W.H. McAnney, and J. Savir, Built-In Test for VLSI, John Wiley&Sons, New York, 1987.
[25] B. Konemann, J. Mucha, and G. Zwiehoff, “Built-In Logic Block Observation Technique,” Digest Papers 1979 Test Conf., pp. 37-41, Oct. 1979.
[26] J. Saul, B. Eschermann, and J. Froessl, “Two-Level Logic Circuits Using EXOR Sums of Products,” IEE Proc., vol. 140, pp. 348-356, Nov. 1993.
[27] B.B. Bhattacharya, B. Gupta, S. Sarkar, and A.K. Choudhury, “Testable Design of RMC Networks with Universal Tests for Detecting Stuck-At and Bridging Faults,” IEE Proc., vol. 132, pp. 155-161, May 1985.

Index Terms:
Universal test set, AND-EXOR realizations, Reed-Muller expressions, single stuck-at fault model, easily testable combinational networks, Design for Testing (DFT), self-testable circuits, Built-in Self-Test (BIST), test pattern generation.
Ugur Kalay, Marek A. Perkowski, Douglas V. Hall, "A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits," IEEE Transactions on Computers, vol. 49, no. 3, pp. 267-276, March 2000, doi:10.1109/12.841130
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