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Accelerating Pipelined Integer and Floating-Point Accumulations in Configurable Hardware with Delayed Addition Techniques
March 2000 (vol. 49 no. 3)
pp. 208-218
ASCII Text
x 
 
Zhen Luo, Margaret Martonosi, "Accelerating Pipelined Integer and Floating-Point Accumulations in Configurable Hardware with Delayed Addition Techniques," IEEE Transactions on Computers, vol. 49, no. 3, pp. 208-218, March, 2000.
 
 
BibTex
x
 
@article{ 10.1109/12.841125,
author = {Zhen Luo and Margaret Martonosi},
title = {Accelerating Pipelined Integer and Floating-Point Accumulations in Configurable Hardware with Delayed Addition Techniques},
journal ={IEEE Transactions on Computers},
volume = {49},
number = {3},
issn = {0018-9340},
year = {2000},
pages = {208-218},
doi = {http://doi.ieeecomputersociety.org/10.1109/12.841125},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Accelerating Pipelined Integer and Floating-Point Accumulations in Configurable Hardware with Delayed Addition Techniques
IS - 3
SN - 0018-9340
SP208
EP218
EPD - 208-218
A1 - Zhen Luo,
A1 - Margaret Martonosi,
PY - 2000
KW - Delayed addition
KW - accumulation
KW - multiply-accumulate
KW - MAC
KW - FPGA.
VL - 49
JA - IEEE Transactions on Computers
ER -
 

Abstract—The speed of arithmetic calculations in configurable hardware is limited by carry propagation, even with the dedicated hardware found in recent FPGAs. This paper proposes and evaluates an approach called delayed addition that reduces the carry-propagation bottleneck and improves the performance of arithmetic calculations. Our approach employs the idea used in Wallace trees to store the results in an intermediate form and delay addition until the end of a repeated calculation such as accumulation or dot-product; this effectively removes carry propagation overhead from the calculation's critical path. We present both integer and floating-point designs that use our technique. Our pipelined integer multiply-accumulate (MAC) design is based on a fairly traditional multiplier design, but with delayed addition as well. This design achieves a 72MHz clock rate on an XC4036xla-9 FPGA and 170MHz clock rate on an XV300epq240-8 FPGA. Next, we present a 32-bit floating-point accumulator based on delayed addition. Here, delayed addition requires a novel alignment technique that decouples the incoming operands from the accumulated result. A conservative version of this design achieves a 40 MHz clock rate on an XC4036xla-9 FPGA and 97MHz clock rate on an XV100epq240-8 FPGA. We also present a 32-bit floating-point accumulator design with compiler-managed overflow avoidance that achieves a 80MHz clock rate on an XC4036xla-9 FPGA and 150MHz clock rate on an XCV100epq240-8 FPGA.

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Index Terms:
Delayed addition, accumulation, multiply-accumulate, MAC, FPGA.
Citation:
Zhen Luo, Margaret Martonosi, "Accelerating Pipelined Integer and Floating-Point Accumulations in Configurable Hardware with Delayed Addition Techniques," IEEE Transactions on Computers, vol. 49, no. 3, pp. 208-218, March 2000, doi:10.1109/12.841125
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