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Sorin Cotofana, Stamatis Vassiliadis, "Signed Digit Addition and Related Operations with Threshold Logic," IEEE Transactions on Computers, vol. 49, no. 3, pp. 193207, March, 2000.  
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@article{ 10.1109/12.841124, author = {Sorin Cotofana and Stamatis Vassiliadis}, title = {Signed Digit Addition and Related Operations with Threshold Logic}, journal ={IEEE Transactions on Computers}, volume = {49}, number = {3}, issn = {00189340}, year = {2000}, pages = {193207}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.841124}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  Signed Digit Addition and Related Operations with Threshold Logic IS  3 SN  00189340 SP193 EP207 EPD  193207 A1  Sorin Cotofana, A1  Stamatis Vassiliadis, PY  2000 KW  Computer arithmetic KW  signeddigit number representation KW  signeddigit arithmetic KW  carryfree addition KW  redundant adders KW  redundant multipliers KW  threshold logic KW  neural networks. VL  49 JA  IEEE Transactions on Computers ER   
Abstract—Assuming signed digit number representations, we investigate the implementation of some addition related operations assuming linear threshold networks. We measure the depth and size of the networks in terms of linear threshold gates. We show first that a depth
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