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New Efficient Structure for a Modular Multiplier for RNS
February 2000 (vol. 49 no. 2)
pp. 170-174

Abstract—Modular multiplication is a very important arithmetic operation in residue-based real-time computing systems. In realizing these multipliers, ROM-based structures are more efficient for small moduli. Due to the exponential growth of ROM sizes, implementations with arithmetic components are more suitable for medium and large moduli. This paper presents a new modular multiplier that can deal efficiently with medium and large size moduli. The design of this modular multiplier that multiplies two $n$ bit residue digits consists, basically, of a $(n\times n)$ binary multiplier, a $((n-1-k)\times k)$ binary multiplier $(k, three $n$-bit adders, and a small-size combinational circuit. When compared with the most competitive published work [12], the new multiplier reduces, significantly, both time delay and hardware requirements. The design is very suitable for VLSI realization.

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Index Terms:
Residue number system, modular multiplication, computer arithmetic, VLSI, hardware requirements, time delay.
Citation:
Ahmad A. Hiasat, "New Efficient Structure for a Modular Multiplier for RNS," IEEE Transactions on Computers, vol. 49, no. 2, pp. 170-174, Feb. 2000, doi:10.1109/12.833113
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