This Article 
 Bibliographic References 
 Add to: 
New Efficient Structure for a Modular Multiplier for RNS
February 2000 (vol. 49 no. 2)
pp. 170-174

Abstract—Modular multiplication is a very important arithmetic operation in residue-based real-time computing systems. In realizing these multipliers, ROM-based structures are more efficient for small moduli. Due to the exponential growth of ROM sizes, implementations with arithmetic components are more suitable for medium and large moduli. This paper presents a new modular multiplier that can deal efficiently with medium and large size moduli. The design of this modular multiplier that multiplies two $n$ bit residue digits consists, basically, of a $(n\times n)$ binary multiplier, a $((n-1-k)\times k)$ binary multiplier $(k, three $n$-bit adders, and a small-size combinational circuit. When compared with the most competitive published work [12], the new multiplier reduces, significantly, both time delay and hardware requirements. The design is very suitable for VLSI realization.

[1] N. Szabo and R. Tanaka, Residue Arithmetic and Its Applications to Computer Technology. New York: McGraw Hill, 1967.
[2] Residue Number System Arithmetic: Modern Applications in Digital Signal Processing, M. Soderstrand, M.AW. Jenkins, G. Jullien, and F. Taylor, eds. NewYork: IEEE Press, 1986.
[3] M. Soderstrand and C. Vernia, “A High-Speed Low-Cost Modulo$P_i$Multiplier with RNS Arithmetic Application,” Proc. IEEE, vol. 68, pp. 529-532, Apr. 1980.
[4] G.A. Jullien, “Implementation of Multiplication, Modulo$a$Prime Number, with Applications to Theoretic Transforms,” IEEE Trans Computers, vol. 29, no. 10, pp. 899-905, Oct. 1980.
[5] D. Radhakrishnan and Y. Yuan, “Novel Approaches to the Design of VLSI RNS Multipliers,” IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 39, pp. 52-57, Jan. 1992.
[6] M. Dugdale, “Residue Multipliers Using Factored Decomposition,” IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 41, pp. 623-627, Sept. 1994.
[7] A.S. Ramnarayan, “Practical Realization of mod$p$,$p$Prime Multiplier,” Electronics Letters, vol. 16, pp. 466-467, June 1980.
[8] F.J. Taylor, “A VLSI Residue Arithmetic Multiplier,” IEEE Trans. Computers, vol. 31, no. 6, pp. 540-546, June 1982.
[9] A. Hiasat, “A Memoryless mod$(2^n\pm 1)$Residue Multiplier,” Electronics Letters, vol. 28, pp. 414-415, Jan. 1991.
[10] M. Parker and M. Benaissa, “VLSI Structures for Bit-Serial Modular Multiplication Using Basis Conversion,” IEE Proc. Computers and Digital Techniques, vol. 141, no. 6, Nov. 1994.
[11] C.D. Walter, “Systolic Modular Multiplier,” IEEE Trans. Computers, vol. 42, no. 3, pp. 376-378, Mar. 1993.
[12] E.D. Claudio et al., Fast Combinatorial RNS Processors for DSP Applications IEEE Trans. Computers, vol. 44, pp. 624-633, 1995.
[13] G. Alia and E. Martinelli, “A VLSI Modulo m Multiplier,” IEEE Trans. Computers, vol. 40, no. 7, pp. 873-878, July 1991.
[14] A. Hiasat, “Semi-Custom VLSI Design for RNS Multipliers Using Combinational Logic Approach,” Proc. IEEE Int'l Conf. Eng. and Computer Systems '96, vol. 2, pp. 935-938, Oct. 1996.
[15] K. Elleithy and M. Bayoumi, “A Systolic Architecture for Modulo Multiplication,” IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 42, pp. 725-729, Nov. 1995.
[16] A. Wrzyszcz, D. Milford, and E. Dagless, “A New Approach to Fixed-Coefficient Inner Product Computation over Finite Rings,” IEEE Trans. Computers, vol. 45, no. 12, pp. 1,345-1,355, Dec. 1996.
[17] J. Bajard, L. Didier, and P. Kornerup, “An RNS Montgomery Modular Multiplication Algorithm,” IEEE Trans. Computers, vol. 47, no. 7, pp. 766-776, July 1998.
[18] K. Elleithy and M. Bayoumi, “Fast and Flexible Architectures for RNS Arithmetic Decoding,” IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 39, pp. 226-235, Apr. 1992.
[19] K. Hwang,Computer Arithmetic, Principles, Architecture, and Design.New York: John Wiley&Sons, 1979.
[20] E.L. Braun, Digital Computer Design. New York: Academic, 1963.
[21] C.S. Wallace, “A Suggestion for a Fast Multiplier,” IEEE Trans. Electronic Computers, vol. 13, pp. 14-17, Feb. 1964.
[22] N. Takagi,H. Yasuura,, and S. Yajima,“High-speed VLSI multiplication algorithm with a redundant binary addition tree,” IEEE Trans. Computers, vol. 34, no. 9, pp. 789-796, Sept. 1985.
[23] B. Sinha and P. Srimani, “Fast Parallel Algorithms for Binary Multiplication and Their Implementation on Systolic Architectures,” IEEE Trans. Computers, vol. 38, no. 3, pp. 424-431, Mar. 1989.
[24] T. Herman, “Linear Algorithms That Are Efficiently Parallelized to Time$O(log\; n)$,” Technical Report TR-85-17, Dept. of Computer Science, Univ. of Texas at Austin, Sept. 1985.

Index Terms:
Residue number system, modular multiplication, computer arithmetic, VLSI, hardware requirements, time delay.
Ahmad A. Hiasat, "New Efficient Structure for a Modular Multiplier for RNS," IEEE Transactions on Computers, vol. 49, no. 2, pp. 170-174, Feb. 2000, doi:10.1109/12.833113
Usage of this product signifies your acceptance of the Terms of Use.