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Area-Efficient VLSI Layouts for Binary Hypercubes
February 2000 (vol. 49 no. 2)
pp. 160-169

Abstract—The hypercube is an interesting and useful topology for parallel computation. While hypercubes have been analyzed in graph theory, this analysis has done little to determine the minimum area required for realizations of the hypercube topology on two-dimensional chips. In a common VLSI layout of the hypercube, the hypercube nodes are placed in a single-row in numeric order. This paper derives an easily computed formula for the minimum number of tracks used by this configuration. For an $n$-node hypercube, the number of tracks required is roughly two-thirds of $n$. This result is also a useful upper bound on the number of tracks required under optimal ordering. In general, the number of tracks required is a function of the ordering, but finding the optimal order (optimal in the sense of requiring the minimum number of tracks over all orderings) is NP-hard. Finally, the formula is applied to more area-efficient and practical two-dimensional hypercube layouts. In general, it allows estimation of and control over implementation parameters such as area and chip aspect ratios.

[1] U.I. Gupta, D.T. Lee, and I.Y.-T. Leung, “Efficient Algorithms for Interval Graphs and Circular Arc Graphs,” Networks, vol. 12, no. 4, pp. 459-467, Winter 1982.
[2] F. Harary, J. Hayes, and H.-J. Wu, “A Survey of the Theory of Hypercube Graphs,” Computers and Math. with Applications, vol. 15, no. 4, pp. 277-289, 1988.
[3] P.C. Kainen, “On the Stable Crossing Number of Cubes,” Proc. Am. Math. Soc., vol. 36, no. 1, pp. 55-62, Nov. 1972.
[4] F.T. Leighton,Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes.San Mateo, Calif.: Morgan Kaufmann, 1992.
[5] C.D. McCrosky, “Message Routing in Synchronous Hypercubes,” Computer Systems Science and Eng., vol. 4, no. 1, pp. 89-96, Jan. 1989.
[6] R.H. Möhring, “Graph Problems Related to Gate Matrix Layout and PLA Folding,” Computing Supplementum 7, pp. 17-51, Springer-Verlag, 1990.
[7] A.G. Ranade and S.L. Johnsson, “The Communication Efficiency of Meshes, Boolean Cubes and Cube Connected Cycles for Wafer Scale Integration,” Proc. 1987 Int'l Conf. Parallel Processing, pp. 479-482, 1987.
[8] O. Wing, S. Huang, and R. Wang, “Gate Matrix Layout,” IEEE Trans. Computer-Aided Design, vol. 4, no. 3, pp. 220-231, July 1985.

Index Terms:
Hypercube, VLSI layout, track assignment.
Citation:
Alpesh Patel, Anthony Kusalik, Carl McCrosky, "Area-Efficient VLSI Layouts for Binary Hypercubes," IEEE Transactions on Computers, vol. 49, no. 2, pp. 160-169, Feb. 2000, doi:10.1109/12.833112
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