
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
Sissades Tongsima, Edwin H.M. Sha, Chantana Chantrapornchai, David R. Surma, Nelson Luiz Passos, "Probabilistic Loop Scheduling for Applications with Uncertain Execution Time," IEEE Transactions on Computers, vol. 49, no. 1, pp. 6580, January, 2000.  
BibTex  x  
@article{ 10.1109/12.822565, author = {Sissades Tongsima and Edwin H.M. Sha and Chantana Chantrapornchai and David R. Surma and Nelson Luiz Passos}, title = {Probabilistic Loop Scheduling for Applications with Uncertain Execution Time}, journal ={IEEE Transactions on Computers}, volume = {49}, number = {1}, issn = {00189340}, year = {2000}, pages = {6580}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.822565}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Probabilistic Loop Scheduling for Applications with Uncertain Execution Time IS  1 SN  00189340 SP65 EP80 EPD  6580 A1  Sissades Tongsima, A1  Edwin H.M. Sha, A1  Chantana Chantrapornchai, A1  David R. Surma, A1  Nelson Luiz Passos, PY  2000 KW  Scheduling KW  loop pipelining KW  probabilistic approach KW  retiming KW  rotation scheduling. VL  49 JA  IEEE Transactions on Computers ER   
Abstract—One of the difficulties in highlevel synthesis and compiler optimization is obtaining a good schedule without knowing the exact computation time of the tasks involved. The uncertain computation times of these tasks normally occur when conditional instructions are employed and/or inputs of the tasks influence the computation time. The relationship between these tasks can be represented as a dataflow graph where each node models the task associated with a probabilistic computation time. A set of edges represents the dependencies between tasks. In this research, we study scheduling and optimization algorithms taking into account the probabilistic execution times. Two novel algorithms, called
[1] A. Aiken and A. Nicolau, “Development Environment for Horizontal Microcode,” IEEE Trans. Software Eng., vol. 14, Feb. 1987.
[2] A. Aiken and A Nicolau,“Optimal loop parallelization,” Proc. 1988 ACM SIGPLAN Conf. Programming Language Design and Implementation, pp. 308317, June 1988.
[3] U. Banerjee, “Unimodular Transformations of Double Loops,” Proc. Workshop Advances in Languages and Compilers for Parallel Processing, pp. 192219, Aug. 1990.
[4] P.P. Chang, S.A. Mahlke, W.Y. Chen, N.J. Warter, and W.W. Hwu, "IMPACT: An Architectural Framework for MultipleIssue Processors," Proc. 18th Ann. Int'l Symp. Computer Architecture, pp. 276275,Toronto, Ontario, Canada, May 1991.
[5] L.F. Chao, A. LaPaugh, and E.H. Sha, "Rotation Scheduling: A Loop Pipelining Algorithm," Proc. ACM/IEEE Design Automation Conf., 1993.
[6] L. Chao and E. Sha, “Static Scheduling for Synthesis of DSP Algorithms on Various Models,” J. VLSI Signal Processing, pp. 207223, Oct. 1995.
[7] A.E. Eichenberger and E.S. Davidson, “Stage Scheduling: A Technique to Reduce the Register Requirements of a Modulo Schedule,” Proc. 28th Int'l Ann. Symp. Microarchitecture, pp. 338349, Nov. 1995.
[8] A.E. Eichenberger, E.S. Davidson, and S.G. Abraham, "Minimum Register Requirements for a Modulo Schedule," Proc. 27th Ann. Int'l Symp. Microarchitecture, pp. 7584,San Jose, Calif., Nov.30 Dec.2, 1994.
[9] J.A. Fisher, “Trace Scheduling: A Technique for Global Microcode Compaction,” IEEE Trans. Computers, vol. 30, no. 7, pp. 478490, July 1981.
[10] I.T. Foster, Designing and Building Parallel Programs AddisonWesley, Reading, Mass., 1995.
[11] R.A. Kamin, G.B. Adams, and P.K. Dubey, “Dynamic ListScheduling with Finite Resources,” Proc. 1994 Int'l Conf. Computer Design, pp. 140144, Oct. 1994.
[12] I. Karkowski and R.H.J.M. Otten, “Retiming Synchronous Circuitry with Imprecise Delays,” Proc. 32nd Design Automation Conf., pp. 322326, 1995.
[13] A.A. Khan, C.L. McCreary, and M.S. Jones, “A Comparison of Multiprocessor Scheduling Heuristics,” Proc. 1994 Int'l Conf. Parallel Processing, vol. II, pp. 243250, 1994.
[14] D.C. Ku and G. De Micheli, High Level Synthesis of ASICs Under Timing and Synchronization Constraints, Kluwer Academic Publishers, Dordrecht, the Netherlands, 1992.
[15] D.C. Ku and G. De Micheli, "Relative Scheduling Under Timing Constraints: Algorithms for HighLevel Synthesis of Digital Circuits," IEEE Trans. ComputerAided Design, vol. 11, June 1992.
[16] M. Lam, "Software Pipelining: An Effective Scheduling Technique for VLIW Machines," Proc. ACM SIGPLAN Conf. Programming Language Design and Implementation, 1988.
[17] D.M. Lavery and W.W. Hwu, “UnrollingBased Optimizations for Modulo Scheduling,” Proc. 28th Int'l Symp. Microarchitechture, pp. 327337, Nov. 1995.
[18] C.E. Leiserson and J.B. Saxe, “Retiming Synchronous Circuitry,” Algorithmica, vol. 6, pp. 535, 1991.
[19] B.P. Lester, The Art of Parallel Programming. Prentice Hall, 1993.
[20] W. Li and K. Pingali,“A singular loop transformation framework based on nonsingularmatrices,” Tech. Report TR921294, Dept. of Computer Science, Cornell University, July 1992.
[21] J. Llosa, M. Valero, and E. Ayguadé, “Heuristics for RegisterConstrained Software Pipelining,” Proc. 29th Int'l Symp. Microarchitecture (MICRO29), pp. 250261, Dec. 1996.
[22] K.K. Parhi and D.G. Messerschmitt, "Static RateOptimal Scheduling of Iterative DataFlow Programs Via Optimum Unfolding," IEEE Trans. Computers, vol. 40, no. 2, pp. 178195, Feb. 1991.
[23] N.L. Passos, E.H.M. Sha, and S.C. Bass, "Loop Pipelining for Scheduling Multidimensional Systems Via Rotation," to appear in Proc. 31st Design Automation Conf.,San Diego, Calif., June 1994.
[24] B.R. Rau and J. Fisher,“Instructionlevel parallel processing: History, overview, and perspective,” J. SuperComputing, vol. 7, nos. 1/2, Jan. 1993.
[25] B.R. Rau and C.D. Glaeser,“Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientificcomputing,” Proc. 14th Ann. Workshop Microprogramming, pp. 183198, Oct. 1981.
[26] B. Ramakrishna Rau, “Iterative Modulo Scheduling: An Slgorithm for Software Pipelining Loops,” Proc. 27th Ann. Int'l Symp. Microarchitecture, pp. 6374, Nov. 1994.
[27] M.E. Wolfe, High Performance Compilers for Parallel Computing, chapter 9. Redwood City, Calif.: AddisonWesley, 1996.
[28] M. Wolf and M. Lam, “A Loop Transformation Theory and an Algorithm to Maximize Parallelism,” IEEE Trans. Parallel and Distributed Systems, vol. 2, no. 4, Oct. 1991.
[29] L.A. Zadeh, “Fuzzy Sets as a Basis for a Theory of Possibility,” Fuzzy Sets and Systems, vol. 1, pp. 328, 1978.