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An Approach for Detecting Multiple Faulty FPGA Logic Blocks
January 2000 (vol. 49 no. 1)
pp. 48-54

Abstract—An approach is proposed to test FPGA logic blocks, including part of the configuration memories used to control them. The proposed AND tree and OR tree-based testing structure is simple and the conditions for constant testability can easily be satisfied. Test generation for only a single logic block is sufficient. We do not assume any particular fault model. Any number of faulty blocks in the chip can be detected. Members of the Xilinx XC3000, XC4000, and XC5200 families were studied. The proposed AND/OR approach was found to reduce the number of FPGA reprogrammings needed for testing by up to a factor of seven versus direct methods of multiple faulty block detection.

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Index Terms:
FPGA, PLD, multiple faults, C-testability, fault tolerance.
Citation:
Wei Kang Huang, Fred J. Meyer, Fabrizio Lombardi, "An Approach for Detecting Multiple Faulty FPGA Logic Blocks," IEEE Transactions on Computers, vol. 49, no. 1, pp. 48-54, Jan. 2000, doi:10.1109/12.822563
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