This Article 
 Bibliographic References 
 Add to: 
An Approach for Detecting Multiple Faulty FPGA Logic Blocks
January 2000 (vol. 49 no. 1)
pp. 48-54

Abstract—An approach is proposed to test FPGA logic blocks, including part of the configuration memories used to control them. The proposed AND tree and OR tree-based testing structure is simple and the conditions for constant testability can easily be satisfied. Test generation for only a single logic block is sufficient. We do not assume any particular fault model. Any number of faulty blocks in the chip can be detected. Members of the Xilinx XC3000, XC4000, and XC5200 families were studied. The proposed AND/OR approach was found to reduce the number of FPGA reprogrammings needed for testing by up to a factor of seven versus direct methods of multiple faulty block detection.

[1] W.K. Huang, F.J. Meyer, and F. Lombardi, “Array-Based Testing of FPGAs: Architecture and Complexity,” Proc. IEEE Innovative Systems in Silicon Conf., pp. 249-258, Oct. 1996.
[2] W.K. Huang, F.J. Meyer, and F. Lombardi, “A XOR-Tree Based Approach for Testing and Diagnosing Configurable FPGAs,” ATS, pp. 248-253, Nov. 1997.
[3] T. Liu, F. Lombardi, and J. Salinas, “Diagnosis of Interconnects and FPICs Using a Structured Walking-1 Approach,” Proc. IEEE VLSI Test Symp., pp. 256-261, 1995.
[4] F. Lombardi, D. Ashen, X.-T. Chen, and W.-K. Huang, “Diagnosing Programmable Interconnect Systems for FPGAs,” Proc. FPGA 96, pp. 100-106, Monterey, Calif., Feb. 1996.
[5] C. Stroud, P. Chen, S. Konala, and M. Abramovici, “Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks,” Proc. FPGA 96, pp. 107-113, Monterey, Calif., Feb. 1996.
[6] C. Stroud, S. Konala, P. Chen, and M. Abramovici, “Built-In Self-Test of Logic Blocks in FPGAs,” Proc. 14th VLSI Test Symp., pp. 387-392, 1996.
[7] C. Stroud, E. Lee, S. Konala, and M. Abramovici, “Using ILA Testing for BIST in FPGAs,” Proc. Int'l Test Conf., 1996.
[8] Xilinx, Inc., The Programmable Gate Array Data Book, San Jose, Calif., 1995.

Index Terms:
FPGA, PLD, multiple faults, C-testability, fault tolerance.
Wei Kang Huang, Fred J. Meyer, Fabrizio Lombardi, "An Approach for Detecting Multiple Faulty FPGA Logic Blocks," IEEE Transactions on Computers, vol. 49, no. 1, pp. 48-54, Jan. 2000, doi:10.1109/12.822563
Usage of this product signifies your acceptance of the Terms of Use.