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Asger Munk Nielsen, David W. Matula, C.n. Lyu, Guy Even, "An IEEE Compliant FloatingPoint Adder that Conforms with the Pipelined PacketForwarding Paradigm," IEEE Transactions on Computers, vol. 49, no. 1, pp. 3347, January, 2000.  
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@article{ 10.1109/12.822562, author = {Asger Munk Nielsen and David W. Matula and C.n. Lyu and Guy Even}, title = {An IEEE Compliant FloatingPoint Adder that Conforms with the Pipelined PacketForwarding Paradigm}, journal ={IEEE Transactions on Computers}, volume = {49}, number = {1}, issn = {00189340}, year = {2000}, pages = {3347}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.822562}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  An IEEE Compliant FloatingPoint Adder that Conforms with the Pipelined PacketForwarding Paradigm IS  1 SN  00189340 SP33 EP47 EPD  3347 A1  Asger Munk Nielsen, A1  David W. Matula, A1  C.n. Lyu, A1  Guy Even, PY  2000 KW  Floatingpoint arithmetic KW  floatingpoint addition KW  IEEE floatingpoint rounding KW  redundant number representations. VL  49 JA  IEEE Transactions on Computers ER   
Abstract—This paper presents a floatingpoint addition algorithm and adder pipeline design employing a packet forwarding pipeline paradigm. The packet forwarding format and the proposed algorithms constitute a new paradigm for handling data hazards in deeply pipelined floatingpoint pipelines. The addition and rounding algorithms employ a four stage execution phase pipeline with each stage suitable for implementation in a short clock period, assuming about 15 logic levels per cycle. The first two cycles are related to addition proper and are the focus of this paper. The last two cycles perform the rounding and have been covered in a paper by Matula and Nielsen [8]. The addition algorithm accepts one operand in a standard binary floatingpoint format at the start of cycle one. The second operand is represented in the packet forwarding floatingpoint format, namely, it is divided into four parts: the sign bit, the exponent string, the principal part of the significand, and the carryround packet. The first three parts of the second operand are input at the start of cycle one and the carryround packet is input at the start of cycle two. The result is output in two formats that both represent the rounded result as required by the IEEE 754 standard. The result is output in the packet forwarding floatingpoint format at the end of cycles two and three to allow forwarding with an effective latency of two cycles. The result is also output in standard IEEE 754 binary format at the end of cycle four for retirement to a register. The packet forwarding result is thus available with an effective two cycle latency for forwarding to the start of the adder pipeline or to a cooperating multiplier pipeline accepting a packet forwarding operand. The effective latency of the proposed design is two cycles for successive dependent operations while preserving IEEE 754 binary floatingpoint compatibility.
[1] ANSI/IEEE Std. 7541985, Binary FloatingPoint Arithmetic, IEEE Press, Piscataway, N.J., 1985 (also called ISO/IEC 559).
[2] M. Daumas and D.W. Matula, “Recoders for Partial Compression and Rounding,” Technical Report RR9701, Ecole Normale Superieure de Lyon, LIP, available athttp://www.enslyon.frLIP.
[3] L. Dadda, V. Piuri, and F. Salice, “Leading Zero Detectors,” Proc. Second Int'l Conf. Massively Parallel Computing Systems, pp. 409416, Ischia, Italy, May 1996.
[4] J. Duprat, Y. Herreros, and J.M. Muller, “Some Results about OnLine Computation of Functions,” Proc. Ninth IEEE Symp. Computer Arithmetic, pp. 112118, Sept. 1989.
[5] M.P. Farmwald, “On the Design of HighPerformance Digital Arithmetic Units,” PhD thesis, Stanford Univ., Aug. 1981.
[6] A. Guyot, B. Hochet, and J.M. Muller, “JANUS, an OnLine Multiplier/Divider for Manipulating Large Numbers,” Proc. Ninth IEEE Symp. Computer Arithmetic, pp. 106111, Sept. 1989.
[7] C.N. Lyu, “MicroArchitecture of a Pipelined FloatingPoint Execution Unit,” PhD thesis, Southern Methodist Univ., Dallas, Tex., Dec. 1995.
[8] D.W. Matula and A.M. Nielsen, “Pipelined PacketForwarding Floating Point: I. Foundations and a Rounder,” Proc. 13th IEEE Symp. Computer Arithmetic, pp. 140147, Asilomar, Calif., July 1997.
[9] Microprocessor Report, various issues, 19941997.
[10] A.M. Nielsen, “Number Systems and Digital Serial Arithmetic,” PhD thesis, Odense Univ., Denmark, Aug. 1997.
[11] S. Oberman, H. AlTwaijry, and M. Flynn, The SNAP Project: Design of Floating Point Arithmetic Units Proc. 13th IEEE Symp. Computer Arithmetic, pp. 156165, 1997.
[12] N.T. Quach and M.J. Flynn, “An Improved Algorithm for HighSpeed FloatingPoint Addition, Technical Report CSLTR9442, Stanford Univ., 1990.
[13] N.T. Quach and M.J. Flynn, “Design and Implementation of the SNAP FloatingPoint Adder,” Technical Report CSLTR91501, Stanford Univ., Dec. 1991. (available athttp://umunhum.stanford.edumain.html).