This Article 
 Bibliographic References 
 Add to: 
An IEEE Compliant Floating-Point Adder that Conforms with the Pipelined Packet-Forwarding Paradigm
January 2000 (vol. 49 no. 1)
pp. 33-47

Abstract—This paper presents a floating-point addition algorithm and adder pipeline design employing a packet forwarding pipeline paradigm. The packet forwarding format and the proposed algorithms constitute a new paradigm for handling data hazards in deeply pipelined floating-point pipelines. The addition and rounding algorithms employ a four stage execution phase pipeline with each stage suitable for implementation in a short clock period, assuming about 15 logic levels per cycle. The first two cycles are related to addition proper and are the focus of this paper. The last two cycles perform the rounding and have been covered in a paper by Matula and Nielsen [8]. The addition algorithm accepts one operand in a standard binary floating-point format at the start of cycle one. The second operand is represented in the packet forwarding floating-point format, namely, it is divided into four parts: the sign bit, the exponent string, the principal part of the significand, and the carry-round packet. The first three parts of the second operand are input at the start of cycle one and the carry-round packet is input at the start of cycle two. The result is output in two formats that both represent the rounded result as required by the IEEE 754 standard. The result is output in the packet forwarding floating-point format at the end of cycles two and three to allow forwarding with an effective latency of two cycles. The result is also output in standard IEEE 754 binary format at the end of cycle four for retirement to a register. The packet forwarding result is thus available with an effective two cycle latency for forwarding to the start of the adder pipeline or to a cooperating multiplier pipeline accepting a packet forwarding operand. The effective latency of the proposed design is two cycles for successive dependent operations while preserving IEEE 754 binary floating-point compatibility.

[1] ANSI/IEEE Std. 754-1985, Binary Floating-Point Arithmetic, IEEE Press, Piscataway, N.J., 1985 (also called ISO/IEC 559).
[2] M. Daumas and D.W. Matula, “Recoders for Partial Compression and Rounding,” Technical Report RR97-01, Ecole Normale Superieure de Lyon, LIP, available athttp://www.ens-lyon.frLIP.
[3] L. Dadda, V. Piuri, and F. Salice, “Leading Zero Detectors,” Proc. Second Int'l Conf. Massively Parallel Computing Systems, pp. 409-416, Ischia, Italy, May 1996.
[4] J. Duprat, Y. Herreros, and J.-M. Muller, “Some Results about On-Line Computation of Functions,” Proc. Ninth IEEE Symp. Computer Arithmetic, pp. 112-118, Sept. 1989.
[5] M.P. Farmwald, “On the Design of High-Performance Digital Arithmetic Units,” PhD thesis, Stanford Univ., Aug. 1981.
[6] A. Guyot, B. Hochet, and J.-M. Muller, “JANUS, an On-Line Multiplier/Divider for Manipulating Large Numbers,” Proc. Ninth IEEE Symp. Computer Arithmetic, pp. 106-111, Sept. 1989.
[7] C.-N. Lyu, “Micro-Architecture of a Pipelined Floating-Point Execution Unit,” PhD thesis, Southern Methodist Univ., Dallas, Tex., Dec. 1995.
[8] D.W. Matula and A.M. Nielsen, “Pipelined Packet-Forwarding Floating Point: I. Foundations and a Rounder,” Proc. 13th IEEE Symp. Computer Arithmetic, pp. 140-147, Asilomar, Calif., July 1997.
[9] Microprocessor Report, various issues, 1994-1997.
[10] A.M. Nielsen, “Number Systems and Digital Serial Arithmetic,” PhD thesis, Odense Univ., Denmark, Aug. 1997.
[11] S. Oberman, H. Al-Twaijry, and M. Flynn, The SNAP Project: Design of Floating Point Arithmetic Units Proc. 13th IEEE Symp. Computer Arithmetic, pp. 156-165, 1997.
[12] N.T. Quach and M.J. Flynn, “An Improved Algorithm for High-Speed Floating-Point Addition, Technical Report CSL-TR-9-442, Stanford Univ., 1990.
[13] N.T. Quach and M.J. Flynn, “Design and Implementation of the SNAP Floating-Point Adder,” Technical Report CSL-TR-91-501, Stanford Univ., Dec. 1991. (available athttp://umunhum.stanford.edumain.html).

Index Terms:
Floating-point arithmetic, floating-point addition, IEEE floating-point rounding, redundant number representations.
Asger Munk Nielsen, David W. Matula, C.n. Lyu, Guy Even, "An IEEE Compliant Floating-Point Adder that Conforms with the Pipelined Packet-Forwarding Paradigm," IEEE Transactions on Computers, vol. 49, no. 1, pp. 33-47, Jan. 2000, doi:10.1109/12.822562
Usage of this product signifies your acceptance of the Terms of Use.