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Mitrajit Chatterjee, Savita Banerjee, Dhiraj K. Pradhan, "Buffer Assignment Algorithms on Data Driven ASICs," IEEE Transactions on Computers, vol. 49, no. 1, pp. 1632, January, 2000.  
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@article{ 10.1109/12.822561, author = {Mitrajit Chatterjee and Savita Banerjee and Dhiraj K. Pradhan}, title = {Buffer Assignment Algorithms on Data Driven ASICs}, journal ={IEEE Transactions on Computers}, volume = {49}, number = {1}, issn = {00189340}, year = {2000}, pages = {1632}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.822561}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  Buffer Assignment Algorithms on Data Driven ASICs IS  1 SN  00189340 SP16 EP32 EPD  1632 A1  Mitrajit Chatterjee, A1  Savita Banerjee, A1  Dhiraj K. Pradhan, PY  2000 KW  Application specific integrated circuits KW  data driven architecture KW  data flow graph KW  throughput KW  buffers KW  wavepipelining. VL  49 JA  IEEE Transactions on Computers ER   
Abstract—Data driven architectures have significant potential in the design of high performance ASICs. By exploiting the inherent parallelism in the application, these architectures can maximize pipelining. The key consideration involved with the design of a data driven ASIC is ensuring that throughput is maximized while a relatively low area is maintained. Optimal throughput can be realized by ensuring that all operands arrive simultaneously at their corresponding operator node. If this condition is achieved, the underlying data flow graph is said to be balanced. If the initial data flow graph is unbalanced, buffers must be inserted to prevent the clogging of the pipeline along the shorter paths. A novel algorithm for the assignment of buffers in a data flow graph is proposed. The method can also be applied to achieve wavepipelining in digital systems under certain restrictions. The algorithm uses a new application of the retiming technique; the number of buffers here is shown to be equal to the minimum number of buffers achieved by integer programming techniques. We also discuss an extension of this algorithm which can further reduce the number of buffers by altering the DFG without affecting functionality or performance. The time complexities of the proposed algorithms are O(
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