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Buffer Assignment Algorithms on Data Driven ASICs
January 2000 (vol. 49 no. 1)
pp. 16-32

Abstract—Data driven architectures have significant potential in the design of high performance ASICs. By exploiting the inherent parallelism in the application, these architectures can maximize pipelining. The key consideration involved with the design of a data driven ASIC is ensuring that throughput is maximized while a relatively low area is maintained. Optimal throughput can be realized by ensuring that all operands arrive simultaneously at their corresponding operator node. If this condition is achieved, the underlying data flow graph is said to be balanced. If the initial data flow graph is unbalanced, buffers must be inserted to prevent the clogging of the pipeline along the shorter paths. A novel algorithm for the assignment of buffers in a data flow graph is proposed. The method can also be applied to achieve wave-pipelining in digital systems under certain restrictions. The algorithm uses a new application of the retiming technique; the number of buffers here is shown to be equal to the minimum number of buffers achieved by integer programming techniques. We also discuss an extension of this algorithm which can further reduce the number of buffers by altering the DFG without affecting functionality or performance. The time complexities of the proposed algorithms are O($V \times E$) and O($V^2 \times$logV), respectively, a considerable improvement over the existing strategies. Also proposed is a novel buffer distribution algorithm that exploits a unique feature of data driven operation. This procedure maximizes throughput by inserting substantially fewer buffers than other techniques. Experimental results show that the proposed algorithms outperform the existing methods.

[1] S.Y. Kung, VLSI Array Processors. Prentice Hall, 1988.
[2] J.L. Gaudiot and L. Bic, Advanced Topics in Data-Flow Computing. Prentice Hall, 1991.
[3] T.H.Y. Meng, Synchronization Design for Digital Systems. Boston: Kluwer Academic, 1991.
[4] P.R. Chang and C.S.G. Lee, “A Decomposition Approach for Balancing Large-Scale Acyclic Data Flow Graphs,” IEEE Trans. Computers, vol. 39, no. 1, pp. 34-46, Jan. 1990.
[5] E. Boros, P.L. Hammer, and R. Shamir, “A Polynomial Algorithm for Balancing Acyclic Data Flow Graphs,” IEEE Trans. Computers, vol. 41, no. 11, pp. 1,380-1,385, Nov. 1992.
[6] J.D. Brock and L.B. Montz, “Translation and Optimization of Data Flow Programs,” Proc. 1979 Int'l Conf. Parallel Processing, pp. 46-54, Aug. 1979.
[7] J.B. Dennis and G.R. Gao, “Maximum Pipelining of Array Operations on Static Data Flow Machine,” Proc. 1983 Int'l Conf. Parallel Processing, pp. 331-334, 1983.
[8] K.W. Yeung, “A Data-Driven Multiprocessor Architecture for High Throughput Digital Signal Processing,” PhD thesis, Electronics Research Laboratory, College of Eng., Univ. of California, Berkeley, July 1995.
[9] A.K. Yeung and J. Rabaey, “A Data-Driven Architecture for Rapid Prototyping of High Throughput DSP Algorithms,” Proc. IEEE Signal Processing Workshop, Oct. 1992.
[10] U. Schmidt, “Data-Wave: A Data Driven Video Signal Array Processor,” Proc. Hot Chips II: Symp. High Performance Chips, Aug. 1990.
[11] I. Koren et al., “A Data-Driven VLSI Array for Arbitrary Algorithms,” Computer, Oct. 1988.
[12] M.C. McFarland, A.C. Parker, and R. Camposano, "The High-Level Synthesis of Digital Systems," Proc. IEEE, vol. 78, Feb. 1990.
[13] C.E. Leiserson and J.B. Saxe, “Retiming Synchronous Circuitry,” Algorithmitica, pp. 5-35, 1991.
[14] C.E. Leiserson and J.B. Saxe, “Optimizing Synchronous Systems” J. VLSI and Computing, vol. 1, no. 1, pp. 41-67, 1983.
[15] B. Patel, “High Level Synthesis of Data Driven ASICs,” PhD dissertation, Electrical and Computer Eng. Dept., Univ. of Massachusetts, Amherst, 1990.
[16] B. Mendelson and G.M. Silberman, “Mapping Data Flow Programs on a VLSI Array of Processors,” Proc. Intl. Symp. Computer Architecture, 1987.
[17] D.K. Pradhan, M. Chatterjee, and S. Banerjee, “Buffer Assignment on Data Driven Architectures,” Proc. Int'l Conf. Computer-Aided Design, pp. 665-668, Santa Clara, Calif., 1993.
[18] M. Chatterjee, S. Banerjee, and D.K. Pradhan, “Node Selection and Buffer Assignment in Data Driven ASICs,” Technical Report 94-049, Dept. of Computer Science, Texas A&M Univ., 1994.
[19] H.A. Taha, Integer Programming—Theory, Applications and Computations. New York: Academic Press, 1975.
[20] G.L. Nemhauser and L.A. Wolsey, Integer and Combinatorial Optimization. New York: Wiley, 1988.
[21] J.B. Dennis, “Data Flow Supercomputers,” Computer, pp. 48-56, Nov. 1980.
[22] H.T. Kung and M. Lam, “Wafer Scale Integration and Two Level Pipelined Implementation of Systolic Arrays,” J. Parallel and Distributed Computing, vol. 1, no. 1, pp 32-63, Sept. 1984.
[23] VLSI and Modern Signal Processing, S.Y. Kung, H.J. Whitehouse, and T. Kailath, eds., Englewood Cliffs, N.J.: Prentice Hall, 1985.
[24] J.L. Bentley, D. Haken, and J.B. Saxe, “A General Method for Solving Divide and Conquer Recurrences,” SIGACT News, vol. 12, no. 3, pp. 36-44, 1980.
[25] S. Baase, Computer Algorithms—Introduction to Design and Analysis. Reading, Mass.: Addison-Wesley, 1989.
[26] B. Patel, D.K. Pradhan, and I. Koren, “High-Level Synthesis of Data-Driven ASICs,” Proc. TECHCON, 1990.
[27] M. Pedram and J. Rabaey, “Design Solutions and Challenges for Low Power Systems,” Tutorial 2 Notes, Proc. Int'l Conf. Computer-Aided Design, 1994.
[28] A.C. Parker, J. Pizarro, and M.J. Mlinar, "MAHA: A Program for Datapath Synthesis," Proc. ACM/IEEE Design Automation Conf., 1986.
[29] N.V. Shenoy et al., “Minimum Padding to Satisfy Short Path Constraints,” Proc. Int'l Conf. Computer-Aided Design, pp. 156-161, Santa Clara, Calif., 1993.
[30] D. Wong, G. De Micheli, and M. Flynn, “Inserting Active Delay Elements to Achieve Wave Pipelining,” Proc. Int'l Conf. Computer-Aided Design, pp. 270-273, Santa Clara, Calif., 1989.
[31] C.H. Gebotys and M.I. Elmasry, Optimal VLSI Architectural Synthesis—Area, Performance and Testability. Boston: Kluwer Academic, 1992.
[32] C. Mead and L. Conway, Introduction to VLSI Systems, Addison-Wesley, Reading, Mass., 1980.

Index Terms:
Application specific integrated circuits, data driven architecture, data flow graph, throughput, buffers, wave-pipelining.
Citation:
Mitrajit Chatterjee, Savita Banerjee, Dhiraj K. Pradhan, "Buffer Assignment Algorithms on Data Driven ASICs," IEEE Transactions on Computers, vol. 49, no. 1, pp. 16-32, Jan. 2000, doi:10.1109/12.822561
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