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Distributed Generation of Weighted Random Patterns
December 1999 (vol. 48 no. 12)
pp. 1364-1368

Abstract—This paper describes the design details, operation, cost, and performance of a distributed weighted pattern test approach at the chip level. The traditional LSSD SRLs are being replaced by WRP SRLs designed specifically to facilitate a weighted random pattern (WRP) test. A two-bit code is transmitted to each WRP SRL to determine its specific weight. The WRP test is then divided into groups, where each group is activated with a different set of weights. The weights are dynamically adjusted during the course of the test to “go after” the remaining untested faults. The cost and performance of this design system are explored on ten pilot chips. Results of this experiment are provided in the paper.

[1] M.F. AlShaibi and C.R. Kime, “Fixed-Biased Pseudorandom Built-In Self-Test for Random Pattern Resistant Circuits,” Proc. Int'l Test Conf., pp. 929-938, Oct. 1994.
[2] P.H. Bardell, W.H. McAnney, and J. Savir, Built-In Test for VLSI, John Wiley&Sons, New York, 1987.
[3] M. Bershteyn, Calculation of Multiple Sets of Weights for Weighted Random Testing Proc. Int'l Test Conf., pp. 1031-1040, 1993.
[4] F. Brglez, C.S. Gloster, and G. Kedem, "Hardware-Based Weighted Random Pattern Generation for Boundary Scan," Proc. Int'l Test Conf., pp. 264-274. IEEE, 1989.
[5] E.B. Eichelberger and E. Lindbloom, “Random Pattern Coverage Enhancement and Diagnosis for LSSD Logic Self-Test,” IBM J. Research and Development, vol. 27, no. 3, pp. 265-272, May 1983.
[6] C. Gloster, “Synthesis for BIST with PREWARP,” Third Ann. OASIS Research Review, May 1990.
[7] J. Hartmann and G. Kemnitz, How to Do Weighted Random Testing for BIST Proc. Int'l Conf. Computer-Aided Design (ICCAD), 1993.
[8] R. Kapur et al., "Design of an Efficient Weighted Random Pattern Generation System," Proc. Int'l Test Conf., IEEE CS Press, Los Alamitos, Calif., 1994, pp. 491-500.
[9] A. Majumdar, “A Tool for Evaluation and Optimization of Weights for Weighted Random Pattern Testing,” Proc. Int'l Conf. Computer Design, pp. 288-291, 1994.
[10] W.H. McAnney and J. Savir, “Distributed Generation of Non-Uniform Patterns for Circuit Testing,” IBM Technical Disclosure Bulletin, vol. 31, no. 5, pp. 113-116, Oct. 1988.
[11] M.A. Miranda and C.A. Lopez-Barrio, “Generation of Optimal Single Distributions of Weighted Random BIST,” Proc. Int'l Test Conf., pp. 1,023-1,030, Oct. 1993.
[12] F. Muradali, V.K. Agarwal, and B. Nadeau-Dostie, A New Procedure for Weighted Random Built-In-Self-Test Proc. Int'l Test Conf., pp. 660-668, 1990,
[13] F. Muradali, T. Nishida, and T. Shimizu, "A Structure and Technique for Pseudorandom-Based Testing of Sequential Circuits," J. Electronic Testing: Theory and Application, vol. 6, pp. 107-115, 1995.
[14] D.J. Neebel and C.R. Kime, "Inhomogeneous Cellular Automata for Weighted Random Pattern Generation," Proc. Int'l Test Conf., pp. 1,013-1,022. IEEE, 1993.
[15] S. Pateras and J. Rajski, Cube-Contained Random Patterns and Their Application to the Complete Testing of Synthesized Multi-Level Circuits Proc. Int'l Test Conf., pp. 473-481, 1991.
[16] I. Pomeranz and S.M. Reddy, “3-Weight Pseudo-Random Test Generation Based on a Deterministic Test Set for Combinational and Sequential Circuits,” IEEE Trans. Computer-Aided Design, vol. 12, no. 7, pp. 1,050-1,058, July 1993.
[17] B. Reeb and H.J. Wunderlich, “Deterministic Pattern Generation for Weighted Random Pattern Testing,” Proc. European Design and Test Conf., pp. 30-36, Mar. 1996.
[18] J. Savir, "Improved Cutting Algorithm," IBM J. Research&Development, vol. 34, nos. 2/3, pp. 381-388, Mar./May 1990.
[19] J. Savir, “Module Level Weighted Random Patterns,” Proc. Asian Test Symp., pp. 274-278, 1995.
[20] J. Savir, “Module Level Weighted Random Patterns,” J. Electronic Testing, vol. 10, no. 3, pp. 283-287, June 1997.
[21] J. Savir, G.S. Ditlow, and P.H. Bardell, “Random Pattern Testability,” IEEE Trans. Computers, vol. 33, no. 1, pp. 79-90, Jan. 1984.
[22] H.D. Schnurmann, E. Lindbloom, and R.G. Carpenter, “The Weighted Random Test Pattern Generator,” IEEE Trans. Computers, vol. 24, no. 7, pp. 695-700, July 1975.
[23] C. Schotten and H. Meyr, “Test Point Insertion for an Area Efficient BIST,” Proc. Int'l Test Conf., pp. 515-523, Oct. 1995.
[24] B.H. Seiss, P.M. Trouorst, and M.H. Schulz, “Test Point Insertion for Scan-Based BIST,” Proc. European Test Conf., pp. 253-262, 1991.
[25] N. Tamarapalli and J. Rajski, "Constructive Multi-Phase Test Point Insertion for Scan-Based BIST," Proc. Int'l Test Conf., pp. 649-658, 1996.
[26] N.A. Touba and E.J. McCluskey, “Test Point Insertion Based on Path Tracing,” Proc. VLSI Test Symp., pp. 2-9, Apr. 1996.
[27] J.A. Waicukauski and E. Lindbloom, Fault Detection Effectiveness of Weighted Random Patterns Proc. Int'l Test Conf., pp. 245-261, 1988.
[28] J.A. Waicukauski et al., "A Method for Generating Weighted Random Patterns," IBM J. Research and Development, Vol. 33, Mar., 1989, pp. 149-161.
[29] H.-J. Wunderlich, "PROTEST: A Tool for Probabilistic Testability Analysis," Design Automation Conf. Proc., pp. 204-211. IEEE/ACM, 1985.
[30] H.J. Wunderlich, “Multiple Distributions for Biased Random Test Patterns,” Proc. Int'l Test Conf., pp. 236-244, Oct. 1988.
[31] H.J. Wunderlich, “Self-Test Using Unequiprobable Random Patterns,” Proc. Fault-Tolerant Computing Symp., pp. 258-263, 1988.
[32] J.T. Yen, M. Sullivan, C. Montemayor, W. Pete, and R. Evers, “Overview of PowerPC 620 Multiprocessor Verification Strategy,” Proc. Int'l Test Conf., pp. 167-174, Oct. 1995.

Index Terms:
LSSD, SRL, BIST, WRP, signal probability, detection probability.
Jacob Savir, "Distributed Generation of Weighted Random Patterns," IEEE Transactions on Computers, vol. 48, no. 12, pp. 1364-1368, Dec. 1999, doi:10.1109/12.817399
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