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Issue No.10 - October (1999 vol.48)
pp: 1145-1152
ABSTRACT
<p><b>Abstract</b>—Test generation procedures based on genetic optimization were shown to be effective in achieving high fault coverage for benchmark circuits. In this work, we propose a representation of test patterns for genetic optimization based test generation, where subsets of inputs are considered as indivisible entities. Using this representation, crossover between two test patterns <tmath>$t_1$</tmath> and <tmath>$t_2$</tmath> copies all the values of each subset either from <tmath>$t_1$</tmath> or from <tmath>$t_2$</tmath>. By keeping input subsets undivided, activation and propagation capabilities of <tmath>$t_1$</tmath> and <tmath>$t_2$</tmath> are expected to be captured and carried over to the new test patterns. Experimental results presented show that the proposed scheme results in complete stuck-at test sets and <tmath>$n$</tmath>-detection test sets for combinational circuits, even in cases where other procedures report incomplete fault coverages.</p>
INDEX TERMS
Combinational circuits, genetic optimization, test generation.
CITATION
Irith Pomeranz, Sudhakar M. Reddy, "A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n$n$-Detections in Combinational Circuits", IEEE Transactions on Computers, vol.48, no. 10, pp. 1145-1152, October 1999, doi:10.1109/12.805164