This Article 
 Bibliographic References 
 Add to: 
An Easy-to-Use Approach for Practical Bus-Based System Design
August 1999 (vol. 48 no. 8)
pp. 780-793

Abstract—We present an easy-to-use model that addresses the practical issues in designing bus-based shared-memory multiprocessor systems. The model relates the shared-bus width, bus cycle time, cache memory, the features of a program execution, and the number of processors on a shared bus to a metric called request utilization. The request utilization is treated as the scaling factor for the effective average waiting processors in computing the queuing delay cycles. Simulation study shows that the model performs very well in estimating the shared bus response time. Using the model, a system designer can quickly decide the number of the processors that a shared bus is able to support effectively, the size of the cache memory a system should use, and the bus cycle time that the main memory system should provide. With the model, we show that the design favors caching the requests for a contention-based medium instead of speeding up the transfers although the same performance can be respectively achieved by the two techniques in a contention-free situation.

[1] M. Rosenblum, S. Herrod, E. Witchel, and A. Gupta, "Complete Computer System Simulation," IEEE Parallel and Distributed Technology, Fall 1995.
[2] C.A. Prete, G. Prina, and L. Ricciardi, "A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems," IEEE Trans. Parallel and Distributed Systems, Vol. 6, No. 9, Sept. 1995, pp. 915-929.
[3] D. Thiebaut, "Synthetic Traces for Trace-Driven Simulation of Cache Memories," IEEE Trans. Computers, vol. 41, no. 4, pp. 388-410, Apr. 1992.
[4] R. Giorgi, C. Prete, G. Prina, and L. Ricciardi, “A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors,” Proc. 22nd EuroMicro Int'l. Conf., pp. 207-214, Prague, Sept. 1996.
[5] B.L. Bodnar and A.C. Liu, “Modeling and Performance Analysis of Single-Bus Tightly-Coupled Multiprocessors,” IEEE Trans. Computers, vol. 38, no. 3, pp. 464-470, Mar. 1989.
[6] M.K. Vernon, E.D. Lazowska, and J. Zahorjan, “An Accurate and Efficient Performance Analysis Technique for Multiprocessor Snooping Cache-Consistency Protocols,” Proc. 15th Ann. Int'l Symp. Computer Architecture, pp. 308–315, May 1988.
[7] M.C. Chiang and G.S. Sohi, "Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment," IEEE Trans. Computers, vol. 41, no. 3, pp. 297-317, Mar. 1992.
[8] M.A. Holliday and M.K. Vernon,"Exact Performance Estimates for Multiprocessor Memory and Bus Interference," IEEE Trans. Computers, vol. 36, no. 1, pp. 76-85, Jan. 1987.
[9] A.K. Somani et al., "Proteus System Architecture and Organization," Proc. Fifth Int'l Parallel Processing Symp., pp. 287-294, June 1991. Also, to appear in Machine Vision and Applications, 1993.
[10] S.C. Woo et al., "The SPLASH-2 Programs: Characterization and Methodological Considerations," Proc. 22nd Annual Int'l Symp. Computer Architecture, IEEE CS Press, Los Alamitos, Calif., June 1995, pp. 24-36.
[11] K. Sakamura, R. Sano, and K. Honma, “Introducing Tobus, the System Bus in the TRON Architecture,” IEEE Micro, pp. 47-59, Apr. 1988.
[12] T. Lovett and S. Thakkar, “The Symmetry Multiprocessor System,” Proc. Int'l Conf. Parallel Processing, pp. 303-310, 1988.
[13] S. Thakkar, P. Gifford, and G. Fielland, “The Balance Multiprocessor System,” IEEE Micro, Feb. 1988.
[14] A.J. Smith, "Cache Memories," ACM Computing Surveys, Vol. 14, 1982, pp. 473-540.
[15] J. Hennessy and D. Patterson, Computer Architecture: A Quantitative Approach. Morgan Kaufmann, 1995.
[16] C.-H. Chen, “Exploring the Design Space of Cache Memories, Bus Width, and Burst Transfer Memory Systems,” J. Chinese Inst. of Engineers, vol. 21, no. 3, pp. 269-282, 1998.
[17] E.D. Lazowska, J. Zahorjan, G.S. Graham, and K.C. Sevcik, Quantitative System Performance, Prentice Hall, pp 64-66, 1984.
[18] A. Sharma, N.-T. Nguyen, and J. Torrellas, “Augmint—A Multiprocessor Simulation Environment for Intel x86 Architectures,” CRD Technical Report 1463, Univ. of Illinois at Urbana-Champaign, 1995.
[19] C.-H. Chen and A.K. Somani, “A Unified Architectural Tradeoff Methodology,” Proc. 21st Int'l Symp. Computer Architecture, pp. 348-357, Apr. 1994.
[20] C.-H. Chen and A.K. Somani, “Architecture Technique Trade-Offs Using Mean Memory Delay Time,” IEEE Trans. Computers, vol. 45, no. 10, pp. 1,089-1,100, Oct. 1996.

Index Terms:
Bus-based shared-memory multiprocessor, memory system design, queuing delay model, system design.
Chung-Ho Chen, Feng-Fu Lin, "An Easy-to-Use Approach for Practical Bus-Based System Design," IEEE Transactions on Computers, vol. 48, no. 8, pp. 780-793, Aug. 1999, doi:10.1109/12.795121
Usage of this product signifies your acceptance of the Terms of Use.