This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting
August 1999 (vol. 48 no. 8)
pp. 769-779

Abstract—In high-performance systems, variable-latency units are often employed to improve the average throughput when the worst-case delay exceeds the cycle time. Traditionally, units of this type have been hand-designed. In this paper, we propose a technique for the automatic synthesis of variable-latency units that is applicable to large data-path modules. We define and study an optimization problem, timed supersetting, whose solution is at the kernel of the procedure for automatic generation of variable-latency units. We contribute a new algorithm for solving timed supersetting in the most difficult case, that is, when the timing behavior of the circuit is expressed through an accurate delay model. The proposed solution overcomes the computational limitations of previous approaches and its robustness is experimentally demonstrated by obtaining high-throughput, variable-latency implementations for all the largest circuits in the Iscas '85 and Iscas '89 benchmark suites, as well as for some realistic, high-performance arithmetic units.

[1] S.F. Oberman and M.J. Flynn, “Design Issues in Division and Other Floating Point Operations,” IEEE Trans. Computers, vol. 46, no. 2, pp. 154-161, Feb. 1997.
[2] L. Benini, G. De Micheli, E. Macii, and M. Poncino, “Telescopic Units: A New Paradigm for Performance Optimization of VLSI Designs,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 3, pp. 220-232, Mar. 1998.
[3] R.I. Bahar, E.A. Frohm, C.M. Gaona, G.D. Hachtel, E. Macii, A. Pardo, and F. Somenzi, “Algebraic Decision Diagrams and Their Applications,” Formal Methods in System Design, vol. 10, pp. 171-206, 1997.
[4] R.I. Bahar, H. Cho, G.D. Hachtel, E. Macii, F. Somenzi, “Symbolic Timing Analysis and Re-Synthesis for Low Power of Combinational Circuits Containing False Paths,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 10, pp. 1,101-1,115 Oct. 1997.
[5] P.C. McGeer and R.K. Brayton, Integrating Functional and Temporal Domains in Logic Synthesis. Boston, Mass.: Kluwer Academic, 1991.
[6] F. Brglez and H. Fujiwara, “A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran,” Proc. ISCAS-85: IEEE Int'l Symp. Circuits and Systems, pp. 785-794, Kyoto, Japan, June 1985.
[7] F. Brglez, D. Bryan, and K. Kozminski, "Combinatorial Profiles of Sequential Benchmark Circuits," Proc. IEEE Int'l. Symp. Circuits and Systems, IEEE Computer Soc. Press, Los Alamitos, Calif., 1989, pp. 1929-1934.
[8] T.H. Cormen,C.E. Leiserson, and R.L. Rivest,Introduction to Algorithms.Cambridge, Mass.: MIT Press/McGraw-Hill, 1990.
[9] R.E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Trans. Computers, Vol. C-35, No. 8, Aug. 1986, pp. 667-690.
[10] R.E. Bryant, "Symbolic Boolean Manipulation with Ordered Binary-Decision Diagrams," ACM Computing Surveys, vol., 24 no. 3, pp. 293-318, 1992.
[11] D. Brand and V.S. Iyengar, “Timing Analysis Using Functional Analysis,” Proc. ICCAD-86: Int'l Conf. Computer-Aided Design, pp. 126-129, Santa Clara, Calif., Nov. 1986.
[12] H.-C. Chen and D.H.C. Du, "Path Sensitization in Critical Path Problem," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 2, pp. 196-207, Feb. 1993.
[13] S. Devadas, K. Keutzer, and S. Malik, “Computation of Floating Mode Delay in Combinational Circuits: Theory and Algorithms,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 12, pp. 1,913-1,923, Dec. 1993.
[14] E M. Sentovich et al., “Sequential circuit design using synthesis and optimization,” IEEE Int’l Conf. on Computer Design, pp. 328–333, Oct. 1992.
[15] F. Somenzi, CUDD: University of Colorado Decision Diagram Package, Release 2.1.2, technical report, Dept. of Electrical and Computer Eng., Univ. of Colorado, Boulder, Apr. 1997.
[16] R.E. Bryant, "On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication," IEEE Trans. Computers, vol. 40, no. 2, pp. 206-213, Feb. 1991.

Index Terms:
Logic synthesis, timing analysis, throughput optimization.
Citation:
L. Benini, G. De Micheli, A. Lioy, E. Macii, G. Odasso, M. Poncino, "Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting," IEEE Transactions on Computers, vol. 48, no. 8, pp. 769-779, Aug. 1999, doi:10.1109/12.795120
Usage of this product signifies your acceptance of the Terms of Use.