Publication 1999 Issue No. 7 - July Abstract - A Systolic Array Implementation of the Feng-Rao Algorithm
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A Systolic Array Implementation of the Feng-Rao Algorithm
July 1999 (vol. 48 no. 7)
pp. 690-706
 ASCII Text x Chih-Wei Liu, Kuo-Tai Huang, Chung-Chin Lu, "A Systolic Array Implementation of the Feng-Rao Algorithm," IEEE Transactions on Computers, vol. 48, no. 7, pp. 690-706, July, 1999.
 BibTex x @article{ 10.1109/12.780877,author = {Chih-Wei Liu and Kuo-Tai Huang and Chung-Chin Lu},title = {A Systolic Array Implementation of the Feng-Rao Algorithm},journal ={IEEE Transactions on Computers},volume = {48},number = {7},issn = {0018-9340},year = {1999},pages = {690-706},doi = {http://doi.ieeecomputersociety.org/10.1109/12.780877},publisher = {IEEE Computer Society},address = {Los Alamitos, CA, USA},}
 RefWorks Procite/RefMan/Endnote x TY - JOURJO - IEEE Transactions on ComputersTI - A Systolic Array Implementation of the Feng-Rao AlgorithmIS - 7SN - 0018-9340SP690EP706EPD - 690-706A1 - Chih-Wei Liu, A1 - Kuo-Tai Huang, A1 - Chung-Chin Lu, PY - 1999KW - Error-correcting codesKW - algebraic-geometric codesKW - Feng-Rao algorithmKW - systolic array.VL - 48JA - IEEE Transactions on ComputersER -

Abstract—An efficient implementation of a parallel version of the Feng-Rao algorithm on a one-dimensional systolic array is presented in this paper by adopting an extended syndrome matrix. Syndromes of the same order, lying on a slant diagonal in the extended syndrome matrix, are scheduled to be examined by a series of cells simultaneously and, therefore, a high degree of concurrency of the Feng-Rao algorithm can be achieved. The time complexity of the proposed architecture is $m+g+1$ by using a series of $t+\lfloor {\frac{g-1}{2}} \rfloor +1$, nonhomogeneous but regular, effective processors, called PE cells, and $g$ trivial processors, called D cells, where $t$ is designed as the half of the Feng-Rao bound. Each D cell contains only delay units, while each PE cell contains one finite-field inverter and, except the first one, one or more finite-field multipliers. Cell functions of each PE cell are basically the same and the overall control circuit of the proposed array is quite simple. The proposed architecture requires, in total, $t+\lfloor {\frac{g-1}{2}} \rfloor +1$ finite-field inverters and ${\frac{(t+\lfloor (g-1)/2 \rfloor)(t+\lfloor (g-1)/2 \rfloor +1)}{2}}$ finite-field multipliers. For a practical design, this hardware complexity is acceptable.

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Index Terms:
Error-correcting codes, algebraic-geometric codes, Feng-Rao algorithm, systolic array.
Citation:
Chih-Wei Liu, Kuo-Tai Huang, Chung-Chin Lu, "A Systolic Array Implementation of the Feng-Rao Algorithm," IEEE Transactions on Computers, vol. 48, no. 7, pp. 690-706, July 1999, doi:10.1109/12.780877