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Parallel Multiplication Using Fast Sorting Networks
June 1999 (vol. 48 no. 6)
pp. 640-645

Abstract—A recent paper describes the use of Svoboda's binary counter in the construction of fast parallel multipliers. The resulting approach was shown to be faster than the conventional Dadda multiplier when the wordlength $N$ was small. Unfortunately, the growth in the number of gates of that method was $O(N^3)$ and the speed was $O(N)$. In this paper, Batcher's bitonic sorting network and other efficient networks replace the Svoboda counter. The asymptotic growth rate in gates of these new methods is $O(N^2 \log^2 N )$, and the speed is $O(\log^2 N)$.

[1] L. Dadda, “Some Schemes for Parallel Multipliers,” Alta Frequenza, vol. 34, pp. 349-356, May 1965.
[2] C.S. Wallace, “A Suggestion for a Fast Multiplier,” IEEE Trans. Electronic Computing, vol. 13, pp. 14-17, Feb. 1964.
[3] Z. Wang, G.A. Jullien, and W.C. Miller, “A New Design Technique for Column Compression Multipliers,” IEEE Trans. Computers, vol. 44, no. 8, pp. 962-970, Aug. 1995.
[4] D. Villeger and V.G. Oklobdzija, “Analysis of Booth Encoding Efficiency in Parallel Multipliers Using Compressors for Reduction of Partial Products,” Proc. IEEE 27th Asilomar Conf. Signals, Systems, and Computer, vol. 1, pp. 781-784, 1993.
[5] V.G. Oklobdzija, D. Villeger, and S.S. Liu, "A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach," IEEE Trans. Computers, vol. 45, no. 3, pp. 294-305, Mar. 1996.
[6] B.C. Drerup and E.E. Swartzlander Jr., “Fast Multiplier Bit-product Matrix Reduction Using Bit-Ordering and Parity Generation,” Proc. Asilomar Conf. Signals, Systems, and Computers, pp. 356-360, 1992.
[7] B.C. Drerup and E.E. Swartzlander Jr., “Fast Multiplier Bit-product Matrix Reduction Using Bit-Ordering and Parity Generation,” J. VLSI Signal Processing, vol. 7, pp. 249-257, 1994.
[8] A. Svoboda, “Adder with distributed control” IEEE Trans. Computers, vol. 19, pp. 749-752, 1970.
[9] T.H. Cormen,C.E. Leiserson, and R.L. Rivest,Introduction to Algorithms.Cambridge, Mass.: MIT Press/McGraw-Hill, 1990.
[10] D. Knuth, The Art of Computer Programming, vol. 3: Sorting and Searching. Addison-Wesley, 1973.
[11] H.S. Stone, “Parallel processing with the perfect shuffle,” IEEE Trans. Computers, vol. 20, no. 2, 1971.

Index Terms:
Parallel multiplier, partial product reduction, Dadda's counter, 4:2 compressor, bitonic sorting network.
Paul D. Fiore, "Parallel Multiplication Using Fast Sorting Networks," IEEE Transactions on Computers, vol. 48, no. 6, pp. 640-645, June 1999, doi:10.1109/12.773800
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