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The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing
June 1999 (vol. 48 no. 6)
pp. 628-639

Abstract—This paper describes the GRD (Genetic Reconfiguration of DSPs) chip, which is evolvable hardware designed for neural network applications. The GRD chip is a building block for the configuration of a scalable neural network hardware system. Both the topology and the hidden layer node functions of a neural network mapped on the GRD chips are dynamically reconfigured using a genetic algorithm (GA). Thus, the most desirable network topology and choice of node functions (e.g., Gaussian or sigmoid function) for a given application can be determined adaptively. This approach is particularly suited to applications requiring the ability to cope with time-varying problems and real-time constraints. The GRD chip consists of a 100Mhz 32-bit RISC processor and 15 33Mhz 16-bit DSPs connected in a binary-tree network. The RISC processor is the NEC V830 which executes mainly the GA. According to chromosomes obtained by the GA, DSP functions and the interconnection among them are dynamically reconfigured. The GRD chip does not need a host machine for this reconfiguration. This is desirable for embedded systems in practical industrial applications. Simulation results on chaotic time series prediction are two orders of magnitude faster than on a Sun Ultra 2.

[1] T. Higuchi, T. Niwa, T. Tanaka, H. Iba, H. Garis, and T. Furuya, “Evolvable Hardware with Genetic Learning,” Proc. Simulation of Adaptive Behavior, 1992.
[2] D.E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning. Reading, Mass.: Addison-Wesley, 1989.
[3] H. Sakanashi, M. Salami, M. Iwata, S. Nakaya, T. Yamauchi, T. Inuo, N. Kajihara, and T. Higuchi, “Evolvable Hardware Chip for High Precision Printer Image Compression,” Proc. 15th Nat'l Conf. Artificial Intelligence (AAAI98), 1998.
[4] M. Murakawa, S. Yoshizawa, I. Kajitani, T. Furuya, M. Iwata, and T. Higuchi, “Hardware Evolution at Function Level,” Proc. Parallel Problem Solving from Nature IV, pp. 62-71, 1996.
[5] E. Fiesler, “Comparative Bibliography of Ontogenic Neural Networks,” Proc. Int'l Conf. Artificial Neural Networks, pp. 793-796, 1994.
[6] CNAPS Server, Preliminary Data Sheet. Adaptive Solutions, Inc., 1992.
[7] M.J.D. Powell, "Radial Basis Functions for Multivariable Interpolation: A Review," Algorithms for Approximation, J.C. Mason and M.G. Cox, eds., Oxford University Press, Oxford, UK, 1987, pp. 143-167.
[8] J. Moody and C.J. Darken, “Fast Learning in Networks of Locally-Tuned Processing Units,” Neural Computation, no. 1, pp. 281-294, 1989.
[9] M. Murakawa, S. Yoshizawa, I. Kajitani, and T. Higuchi, “On-Line Adaptation of Neural Networks with Evolvable Hardware,” Proc. Seventh Int'l Conf. Genetic Algorithms, pp. 792-799, 1997.
[10] M.C. Mackey and L. Glass, “Oscillation and Chaos in Physiological Control Systems,” Science, vol. 197, pp. 287-289, 1977.
[11] J. Proakis, Digital Communications. Prentice Hall, 1988.
[12] B. Widrow and S. Stearns, Adaptive Signal Processing. Englewood Cliffs, N.J.: Prentice-Hall, 1985.
[13] S.U.H. Qureshi, “Adaptive Equalization,” Proc. IEEE, vol. 73, pp. 1,349-1,387, 1985.
[14] S. Chen, G.J. Gibson, F.N. Cowan, and P.M. Grant, “Adaptive Equalization of Finite Non-Linear Channels Using Multilayer Perceptrons,” Signal Processing, vol. 20, no. 2, pp. 107-119, 1990.
[15] S. Chen, G.J. Gibson, F.N. Cowan, and P.M. Grant, “Reconstruction of Binary Signals Using an Adaptive Radial Basis Function Equalizer,” Signal Processing, vol. 22, no. 1, pp. 77-93, 1991.

Index Terms:
Evolvable hardware, digital signal processor, genetic algorithm, neural network, RBF network, time series prediction, nonlinear adaptive equalization
Citation:
Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Xin Yao, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi, "The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing," IEEE Transactions on Computers, vol. 48, no. 6, pp. 628-639, June 1999, doi:10.1109/12.773799
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