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| Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Xin Yao, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi, "The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing," IEEE Transactions on Computers, vol. 48, no. 6, pp. 628-639, June, 1999. | |||
| BibTex | x | ||
| @article{ 10.1109/12.773799, author = {Masahiro Murakawa and Shuji Yoshizawa and Isamu Kajitani and Xin Yao and Nobuki Kajihara and Masaya Iwata and Tetsuya Higuchi}, title = {The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing}, journal ={IEEE Transactions on Computers}, volume = {48}, number = {6}, issn = {0018-9340}, year = {1999}, pages = {628-639}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.773799}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing IS - 6 SN - 0018-9340 SP628 EP639 EPD - 628-639 A1 - Masahiro Murakawa, A1 - Shuji Yoshizawa, A1 - Isamu Kajitani, A1 - Xin Yao, A1 - Nobuki Kajihara, A1 - Masaya Iwata, A1 - Tetsuya Higuchi, PY - 1999 KW - Evolvable hardware KW - digital signal processor KW - genetic algorithm KW - neural network KW - RBF network KW - time series prediction KW - nonlinear adaptive equalization VL - 48 JA - IEEE Transactions on Computers ER - | |||
Abstract—This paper describes the GRD (Genetic Reconfiguration of DSPs) chip, which is evolvable hardware designed for neural network applications. The GRD chip is a building block for the configuration of a scalable neural network hardware system. Both the topology and the hidden layer node functions of a neural network mapped on the GRD chips are dynamically reconfigured using a genetic algorithm (GA). Thus, the most desirable network topology and choice of node functions (e.g., Gaussian or sigmoid function) for a given application can be determined adaptively. This approach is particularly suited to applications requiring the ability to cope with time-varying problems and real-time constraints. The GRD chip consists of a 100Mhz 32-bit RISC processor and 15 33Mhz 16-bit DSPs connected in a binary-tree network. The RISC processor is the NEC V830 which executes mainly the GA. According to chromosomes obtained by the GA, DSP functions and the interconnection among them are dynamically reconfigured. The GRD chip does not need a host machine for this reconfiguration. This is desirable for embedded systems in practical industrial applications. Simulation results on chaotic time series prediction are two orders of magnitude faster than on a Sun Ultra 2.
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