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Issue No.06 - June (1999 vol.48)
pp: 579-590
ABSTRACT
<p><b>Abstract</b>—FPGA-based configurable computing machines are evolving rapidly. They offer the ability to deliver very high performance at a fraction of the cost when compared to supercomputers. The first generation of configurable computers (those with multiple FPGAs connected using a specific interconnect) used statically reconfigurable FPGAs. On these configurable computers, computations are performed by partitioning an entire task into spatially interconnected subtasks. Such configurable computers are used in logic emulation systems and for functional verification of hardware. In general, configurable computers provide the ability to reconfigure rapidly to any desired custom form. Hence, the available resources can be reused effectively to cut down the hardware costs and also improve the performance. In this paper, we introduce the concept of temporal partitioning to partition a task into temporally interconnected subtasks. Specifically, we present algorithms for temporal partitioning and scheduling data flow graphs for configurable computers. We are given a configurable computing unit (RPU) with a logic capacity of <tmath>$S_{RPU}$</tmath> and a computational task represented by an <it>acyclic data flow graph</it><tmath>$G=(V,E)$</tmath>. Computations with logic area requirements that exceed <tmath>$S_{RPU}$</tmath> cannot be completely mapped on a configurable computer (using traditional spatial mapping techniques). However, a <it>temporal partitioning</it> of the data flow graph followed by proper scheduling can facilitate the configurable computer based execution. Temporal partitioning of the data flow graph is a <tmath>$k$</tmath>-way partitioning of <tmath>$G=(V,E)$</tmath> such that each partitioned segment will not exceed <tmath>$S_{RPU}$</tmath> in its logic requirement. Scheduling assigns an execution order to the partitioned segments so as to ensure proper execution. Thus, for each segment in <tmath>$\{ s_1, s_2, \cdots, s_k \}$</tmath>, scheduling assigns a unique ordering <tmath>$s_i \rightarrow j$</tmath>, <tmath>$1 \leq i \leq k$</tmath>, <tmath>$1 \leq j \leq k$</tmath>, such that the computation would execute in proper sequential order as defined by the flow graph <tmath>$G=(V,E)$</tmath>.</p>
INDEX TERMS
Configurable computing, field programmable gate arrays, spatial partitioning, temporal partitioning, scheduling, data flow graphs, reconfigurable computers, high performance computing.
CITATION
Karthikeya M. Gajjala Purna, Dinesh Bhatia, "Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers", IEEE Transactions on Computers, vol.48, no. 6, pp. 579-590, June 1999, doi:10.1109/12.773795