Issue No.06 - June (1999 vol.48)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.773794
<p><b>Abstract</b>—A fundamental feature of Dynamically Reconfigurable FPGAs (DRFPGAs) is that the logic and interconnect are time-multiplexed. Thus, for a circuit to be implemented on a DRFPGA, it needs to be partitioned such that each subcircuit can be executed at a different time. In this paper, the partitioning of sequential circuits for execution on a DRFPGA is studied. To determine how to correctly partition a sequential circuit and what are the costs in doing so, we propose a new gate-level model that handles time-multiplexed computation. We also introduce an enchanced force directed scheduling (FDS) algorithm to partition sequential circuits that finds a correct partition with low logic and communication costs, under the assumption that maximum performance is desired. We use our algorithm to partition seven large <it>ISCAS</it> '89 sequential benchmark circuits. The experimental results show that the enhanced FDS reduces communication costs by 27.5 percent with only a 1.1 percent increase in the gate cost compared to traditional FDS.</p>
Dynamically reconfigurable FPGAs, field programmable gate array, reconfigurable computing, partitioning, sequential circuit, time-mulitplexed FPGA, Dharma, DPGA, force directed scheduling.
"Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs", IEEE Transactions on Computers, vol.48, no. 6, pp. 565-578, June 1999, doi:10.1109/12.773794