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IEEE Transactions on Computers
June 1999 (vol. 48 no. 6)
ISSN: 0018-9340
Table of Contents
PAPERS
Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs
(Abstract)
pp. 565-578
ABSTRACT
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SPECIAL SECTION ON CONFIGURABLE COMPUTING
Guest Editors' Introduction
(Abstract)
Jean-Luc Gaudiot
Fabrizio Lombardi
pp. 553-555
ABSTRACT
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PAPERS
Static and Dynamic Configurable Systems
(Abstract)
Eduardo Sanchez
Moshe Sipper
Jacques-Olivier Haenni
Jean-Luc Beuchat
André Stauffer
Andrés Perez-Uribe
pp. 556-564
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Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers
(Abstract)
Karthikeya M. Gajjala Purna
Dinesh Bhatia
pp. 579-590
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Dynamic Reconfiguration to Support Concurrent Applications
(Abstract)
Jack S.N. Jean
Karen Tomko
Vikram Yavagal
Jignesh Shah
Robert Cook
pp. 591-602
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Synthesis of Application Specific Instructions for Embedded DSP Software
(Abstract)
Hoon Choi
Jong-Sun Kim
Chi-Won Yoon
In-Cheol Park
Seung Ho Hwang
Chong-Min Kyung
pp. 603-614
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A Scan-Based Configurable, Programmable, and Scalable Architecture for Sliding Window-Based Operations
(Abstract)
Claude Thibeault
Guy Bégin
pp. 615-627
ABSTRACT
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The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing
(Abstract)
Masahiro Murakawa
Shuji Yoshizawa
Isamu Kajitani
Xin Yao
Nobuki Kajihara
Masaya Iwata
Tetsuya Higuchi
pp. 628-639
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BRIEF CONTRIBUTIONS
Parallel Multiplication Using Fast Sorting Networks
(Abstract)
Paul D. Fiore
pp. 640-645
ABSTRACT
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