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| Chien-Ming Chen, Chung-Ta King, "Walk-Time Address Adjustment for Improving the Accuracy of Dynamic Branch Prediction," IEEE Transactions on Computers, vol. 48, no. 5, pp. 457-469, May, 1999. | |||
| BibTex | x | ||
| @article{ 10.1109/12.769430, author = {Chien-Ming Chen and Chung-Ta King}, title = {Walk-Time Address Adjustment for Improving the Accuracy of Dynamic Branch Prediction}, journal ={IEEE Transactions on Computers}, volume = {48}, number = {5}, issn = {0018-9340}, year = {1999}, pages = {457-469}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.769430}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Walk-Time Address Adjustment for Improving the Accuracy of Dynamic Branch Prediction IS - 5 SN - 0018-9340 SP457 EP469 EPD - 457-469 A1 - Chien-Ming Chen, A1 - Chung-Ta King, PY - 1999 KW - Branch prediction KW - address adjustment KW - computer architecture KW - compiler optimization KW - superscalar processor. VL - 48 JA - IEEE Transactions on Computers ER - | |||
Abstract—Dynamic branch prediction has been an effective technique for boosting the performance of modern high performance microprocessors. Since hardware predictors only have a limited number of 2-bit counters but programs often have a large, variable number of branches, two branches in the programs may thus be mapped to the same 2-bit counter. Predictions for these two branches may interfere with each other. This, in turn, reduces the prediction accuracy. In this paper, we discuss how a pre-run-time optimization technique, called
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