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Fault-Containment in Cache Memories for TMR Redundant Processor Systems
April 1999 (vol. 48 no. 4)
pp. 386-397

Abstract—Cache data errors read by a processor may cause CPU control flow error and force the system to enter a CPU-cache reintegration process in redundant processor systems. The reintegration process degrades the system performance and reliability. To reduce the occurrences of such an event, we propose a real-time error recovery scheme that provides effective fault-containment for data errors in cache memories. The scheme is based on cache data broadcasting of a dirty line after modification. It effectively exploits the redundancy of a fault-tolerant system using hardware voting. The scheme recovers from erroneous cache data written by a processor with full coverage. This error recovery feature remedies the insufficiency of error-correcting codes that are unable to prevent such an error. In addition, more than 60 percent of cache lines are fully covered for recovery due to errors originated from the cache itself, including unrecoverable ECC errors. The protocol can also be used to speedup the CPU-cache reintegration process for a temporarily failed processor. The performance overhead of the protocol is to broadcast only 2-3 percent of the total memory references.

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Index Terms:
Caches, error detection and recovery, fault-containment, redundant systems, transient faults.
Citation:
Chung-Ho Chen, Arun K. Somani, "Fault-Containment in Cache Memories for TMR Redundant Processor Systems," IEEE Transactions on Computers, vol. 48, no. 4, pp. 386-397, April 1999, doi:10.1109/12.762529
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