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Elizabeth M. Rudnick, Janak H. Patel, "Efficient Techniques for Dynamic Test Sequence Compaction," IEEE Transactions on Computers, vol. 48, no. 3, pp. 323330, March, 1999.  
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@article{ 10.1109/12.754998, author = {Elizabeth M. Rudnick and Janak H. Patel}, title = {Efficient Techniques for Dynamic Test Sequence Compaction}, journal ={IEEE Transactions on Computers}, volume = {48}, number = {3}, issn = {00189340}, year = {1999}, pages = {323330}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.754998}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  Efficient Techniques for Dynamic Test Sequence Compaction IS  3 SN  00189340 SP323 EP330 EPD  323330 A1  Elizabeth M. Rudnick, A1  Janak H. Patel, PY  1999 KW  Automatic test generation KW  compact test sets KW  sequential circuit testing KW  test sequence compaction. VL  48 JA  IEEE Transactions on Computers ER   
Abstract—Dynamic test sequence compaction is an effective means of reducing test application time and often results in higher fault coverages and reduced test generation time as well. Three simulationbased techniques for dynamic compaction of test sequences are described. The first technique uses a fault simulator to remove test vectors from the test sequence generated by a test generator if the vectors are not needed to detect the target fault, considering that the circuit state may be known. The second technique uses genetic algorithms to fill the unspecified bits in a partiallyspecified test sequence in order to increase the number of faults detected by the sequence. The third technique uses test sequences provided by the test generator as seeds in a genetic algorithm, and better sequences are evolved that detect more faults. Significant improvements in test set size, fault coverage, and test generation time have been obtained over previous approaches using combinations of the three techniques.
[1] R. Marlett, "An Effective Test Generation System for Sequential Circuits," Proc. Design Automation Conf., pp. 250256, June 1986.
[2] W.T. Cheng, “The BACK Algorithm for Sequential Test Generation,” Proc. Int’l Conf. Computer Design, IEEE CS Press, 1988, pp. 6669.
[3] T. Niermann and J. Patel, HITEC: A Test Generation Package for Sequential Circuits Proc. European Conf. Design Automation, pp. 214218, 1991.
[4] T. Kelsey, K. Saluja, and S. Lee, "An Efficient Algorithm for Sequential Circuit Test Generation," IEEE Trans. Computers, vol. 42, no. 11, pp. 1,3611,371, Nov. 1993.
[5] M.S. Hsiao, E.M. Rudnick, and J.H. Patel, “Sequential Circuit Test Generation Using Dynamic State Traversal,” Proc. 1997 European Design and Test Conf., pp. 2228, Mar. 1997.
[6] M.H. Schulz, E. Trischler, and T.M. Safert, "Socrates: A Highly Efficient Automatic Test Pattern Generation Systen," IEEE Trans. ComputerAided Design, vol. 7, pp. 126137, Jan. 1988.
[7] M.H. Schulz and E. Auth,“Advanced automatic test pattern generation and redundancy identification techniques,” Dig. Papers, FTCS18, pp. 3035, June 1988.
[8] J.A. Waicukauski, P.A. Shupe, D.J. Giramma, and A. Matin, "ATPG for UltraLarge Structured Designs," Proc. Int'l Test Conf., pp. 4451, Sept. 1990.
[9] M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design. Computer Science Press, 1990.
[10] P. Goel and B.C. Rosales, "Test Generation and Dynamic Compaction of Tests," Digest of Papers 1979 Test Conf., pp. 189192, 1979.
[11] M. Abramovici, J.J. Kulikowski, P.R. Menon, and D.T. Miller, "SMART and FAST: Test Generation for VLSI ScanDesign Circuits," IEEE Design&Test of Computers, vol. 3, no. 4, pp. 4354, Aug. 1986.
[12] I. Pomeranz, L.N. Reddy, and S.M. Reddy, "COMPACTEST: A Method to Generate Compact Test Sets for Combinational Circuits," Proc. 1991 Int'l Test Conf., pp. 194203, Oct. 1991.
[13] S. Kajihara, I. Pomeranz, K. Kinoshita, and S.M. Reddy, "CostEffective Generation of Minimal Test Sets for StuckAt Faults in Combinational Logic Circuits," Proc. Design Automation Conf., pp. 102106, June 1993.
[14] T.M. Niermann, R.K. Roy, J.H. Patel,, and J.A. Abraham, “Test Compaction for Sequential Circuits,” IEEE Trans. ComputerAided Design, vol. 11, no. 2, pp. 260267, Feb. 1992.
[15] I. Pomeranz and S.M. Reddy, On Static Compaction of Test Sequences for Synchronous Sequential Circuits Proc. 33rd Design Automation Conf., pp. 215220, June 1996.
[16] F. Corno, P. Prinetto, M. Rebaudengo, and M. Sonza Reorda, "New Static Compaction Techniques of Test Sequences for Sequential Circuits," Proc. European Design and Test Conf., pp. 3743, Mar. 1997.
[17] M.S. Hsiao, E.M. Rudnick, and J.H. Patel, “Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors,” Proc. VLSI Test Symp., pp. 188195, Apr. 1997.
[18] M.S. Hsiao and S.T. Chakradhar, “State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits,” Proc. Conf. Design Automation and Test in Europe, pp. 577582, Feb. 1998.
[19] I. Pomeranz and S.M. Reddy, “On Generating Compact Test Sequences for Synchronous Sequential Circuits,” Proc. European Design Automation Conf. '95, pp. 105110, Sept. 1995.
[20] S.T. Chakradhar and A. Raghunathan, "Bottleneck Removal Algorithm for Dynamic Compaction and Test Cycles Reduction," Proc. European Design Automation Conf. (EURODAC), Sept. 1995.
[21] A. Raghunathan and S.T. Chakradhar, "Acceleration Techniques for Dynamic Vector Compaction," Proc. Int'l Conf. ComputerAided Design, IEEE CS Press, Los Alamitos, Calif., 1995, pp. 310317.
[22] A. Raghunathan and S.T. Chakradhar, "Dynamic Test Sequence Compaction for Sequential Circuits," Proc. Int'l Conf. VLSI Design, pp. 170173, Jan. 1996.
[23] T.J. Lambert and K.K. Saluja, "Methods for Dynamic Test Vector Compaction in Sequential Test Generation," Proc. Int'l Conf. VLSI Design, pp. 166169, Jan. 1996.
[24] I. Pomeranz and S.M. Reddy, "Dynamic Test Compaction for Synchronous Sequential Circuits Using Static Compaction Techniques," Proc. Int'l Symp. FaultTolerant Computing, pp. 5361, June 1996.
[25] R. Bevacqua, L. Guerrazzi, F. Ferrandi, and F. Fummi, "Implicit Test Sequences Compaction for Decreasing Test Application Cost," Proc. Int'l Conf. Computer Design, pp. 384389, Nov. 1996.
[26] E.M. Rudnick and J.H. Patel, "A Genetic Approach to Test Application Time Reduction for Full Scan and Partial Scan Circuits," Proc. Int'l Conf. VLSI Design, pp. 288293, Jan. 1995.
[27] D.E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning. Reading, Mass.: AddisonWesley, 1989.
[28] E.M. Rudnick, J.H. Patel, G.S. Greenstein,, and T.M. Niermann, “A Genetic Algorithm Framework for Test Generation,” IEEE Trans. ComputerAided Design, vol. 16, no. 9, pp. 1,0341,044, Sept. 1997.
[29] T.M. Niermann, W. Cheng, and J.H. Patel, "PROOFS: A Fast, MemoryEfficient Sequential Circuit Fault Simulator," IEEE Trans. ComputerAided Design, vol. 11, no. 2, pp. 198207, Feb. 1992.
[30] F. Brglez, D. Bryan, and K. Kozminski, "Combinatorial Profiles of Sequential Benchmark Circuits," Proc. IEEE Int'l. Symp. Circuits and Systems, IEEE Computer Soc. Press, Los Alamitos, Calif., 1989, pp. 19291934.