This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
On a New Boolean Function with Applications
March 1999 (vol. 48 no. 3)
pp. 296-310

Abstract—Consider a hypercube of $2^n$ points described by $n$ Boolean variables and a subcube of $2^m$ points, $m \leq n$. As is well-known, the Boolean function with value 1 in the points of the subcube can be expressed as the product (AND) of $n-m$ variables. The standard synthesis of arbitrary functions exploits this property. We extend the concept of subcube to the more powerful pseudocube. The basic set is still composed of $2^m$ points, but has a more general form. The function with value 1 in a pseudocube, called pseudoproduct, is expressed as the AND of $n-m$ EXOR-factors, each containing at most $m+1$ variables. Subcubes are special cases of pseudocubes and their corresponding pseudoproducts reduce to standard products. An arbitrary Boolean function can be expressed as a sum of pseudoproducts (SPP). This expression is in general much shorter than the standard sum of products, as demonstrated on some known benchmarks. The logical network of an $n$-bit adder is designed in SPP, as a relevant example of application of this new technique. A class of symmetric functions is also defined, particularly suitable for SPP representation.

[1] S.B. Akers, “Binary Decision Diagrams,” IEEE Trans. Computers, vol. 27, no. 6, pp. 509-516, June 1978.
[2] R.A. Brualdi and H.J. Ryser,Combinatorial Matrix Theory. Cambridge: Cambridge Univ. Press, 1991.
[3] R.E. Bryant, "Symbolic Boolean Manipulation with Ordered Binary-Decision Diagrams," ACM Computing Surveys, vol., 24 no. 3, pp. 293-318, 1992.
[4] O. Coudert, “Doing Two Level Logic Minimization 100 Times Faster,” Proc. ACM-SIAM Symp. Discrete Algorithms, pp. 112-121, San Francisco, 1995.
[5] M. Davio, J.P. Dechamps, and A. Thayse,Discrete and Switching Functions. New York: McGraw-Hill, 1978.
[6] M.R. Garey and D.S. Johnson,Computers and Intractability. San Francisco: Freeman, 1979.
[7] Z. Kohavi,Switching and Finite Automata Theory. New York: McGraw-Hill, 1970.
[8] H.C. Lai and S. Muroga, “Logic Networks with Minimum Number of NOR (NAND) Gates for Parity Functions of$n$Variables,” IEEE Trans. Computers, vol. 36, no. 2, pp. 157-166, Feb. 1987.
[9] G. Lakuhani, “Minimization of Switching Functions for a Multi-Level EXOR Realization,” Proc. IFIP WG 10.5 Workshop Applications of the Reed-Muller Expansion in Circuit Design, pp. 185-190, 1995.
[10] F. Luccio and L. Pagli, “Normal Matrices, Pseudo-Cubes and Pseudo-Products,” Congressus Numerantium, vol. 127, pp. 33-56, 1997.
[11] P.C. McGeer, J. Sanghavi, R.K. Brayton, and A.L. Sangiovanni-Vincentelli, “ESPRESSO-SIGNATURE: A New Exact Minimizer for Logic Functions,” IEEE Trans. VLSI, vol. 1, no. 4, pp. 432-440, 1993.
[12] D.E. Muller, “Application of Boolean Algebra to Switching Circuit Design and to Error Detection,” IRE Trans. Electronic Computers, vol. 3, pp. 6-12, 1954.
[13] S. Muroga,Logic Design and Switching Theory. New York: Wiley, 1979.
[14] T. Sasao, “Logic Synthesis with EXOR Logic Gates,” Logic Synthesis and Optimization, T. Sasao, ed. Kluwer Academic, 1993.
[15] T. Sasao, "EXMIN2: A Simplification Algorithm for Exclusive-OR Sum-of-Products Expressions for Multiple-Valued-Input Two-Valued-Output Functions," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 5, pp. 621-632, May 1993.
[16] T. Sasao, “Input Variable Assignment and Output Phase Optimization of PLA's,” IEEE Trans. Computers, vol. 33, no. 10, pp. 879-894, Oct. 1984.
[17] T. Sasao, “Representation of Logic Functions Using EXOR Operators,” Representation of Discrete Functions, T. Sasao and M. Fujita, eds. Kluwer Academic, 1996.
[18] A. Tran, “Graphical Method for the Convertion of Minterms to Reed-Muller Coefficients and the Minimization of Exclusive-OR Switching Functions,” IEE Proc. Part E, vol. 134, pp. 93-99, 1987.
[19] C.C. Tsai and M. Marek-Sadovska, “Generalized Reed-Muller Forms as a Tool to Detect Symmetries,” IEEE Trans. Computers, vol. 45, no. 1, pp. 33-40, Jan. 1996.
[20] C.C. Tsai and M. Marek-Sadovska, “Boolean Function Classification via Fixed Polarity Reed-Muller Forms,” IEEE Trans. Computers, vol. 46, no. 2, pp. 173-186, Feb. 1997.
[21] S. Yang,Logic Synthesis and Optimization Benchmarks, User Guide. Microelectronic Center of North Carolina, 1991. Benchmarks available at:ftp://ftp.mcnc.org/pub/benchmark/Benchmark-dirs LGSynth93/.
[22] K. Yano, Y. Sasaki, K. Rikino, and K. Seki, Top-Down Pass-Transistor Logic Design IEEE J. Solid-State Circuits, vol. 31, no. 6, pp. 792-803, 1996.
[23] K. Yasuoka, “A Generation Method for Exor-Sum-of-Products Expressions Using Shared Binary Decision Diagrams,” Logic Synthesis and Optimization, T. Saso, ed. Kluwer Academic, 1993.

Index Terms:
Pseudocube, pseudoproduct, EXOR-factor, Boolean function, algebraic expression, logical design.
Citation:
Fabrizio Luccio, Linda Pagli, "On a New Boolean Function with Applications," IEEE Transactions on Computers, vol. 48, no. 3, pp. 296-310, March 1999, doi:10.1109/12.754996
Usage of this product signifies your acceptance of the Terms of Use.