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| Nigel Topham, Antonio González, "Randomized Cache Placement for Eliminating Conflicts," IEEE Transactions on Computers, vol. 48, no. 2, pp. 185-192, February, 1999. | |||
| BibTex | x | ||
| @article{ 10.1109/12.752660, author = {Nigel Topham and Antonio González}, title = {Randomized Cache Placement for Eliminating Conflicts}, journal ={IEEE Transactions on Computers}, volume = {48}, number = {2}, issn = {0018-9340}, year = {1999}, pages = {185-192}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.752660}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Randomized Cache Placement for Eliminating Conflicts IS - 2 SN - 0018-9340 SP185 EP192 EPD - 185-192 A1 - Nigel Topham, A1 - Antonio González, PY - 1999 KW - Conflict avoidance KW - cache architectures KW - performance evaluation. VL - 48 JA - IEEE Transactions on Computers ER - | |||
Abstract—Applications with regular patterns of memory access can experience high levels of cache conflict misses. In shared-memory multiprocessors conflict misses can be increased significantly by the data transpositions required for parallelization. Techniques such as blocking which are introduced within a single thread to improve locality, can result in yet more conflict misses. The tension between minimizing cache conflicts and the other transformations needed for efficient parallelization leads to complex optimization problems for parallelizing compilers. This paper shows how the introduction of a pseudorandom element into the cache index function can effectively eliminate repetitive conflict misses and produce a cache where miss ratio depends solely on working set behavior. We examine the impact of pseudorandom cache indexing on processor cycle times and present practical solutions to some of the major implementation issues for this type of cache. Our conclusions are supported by simulations of a superscalar out-of-order processor executing the SPEC95 benchmarks, as well as from cache simulations of individual loop kernels to illustrate specific effects. We present measurements of Instructions committed Per Cycle (IPC) when comparing the performance of different cache architectures on whole-program benchmarks such as the SPEC95 suite.
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