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A High-Speed Reduced-Size Adder Under Left-to-Right Input Arrival
January 1999 (vol. 48 no. 1)
pp. 76-80

Abstract—An efficient parallel adder under left-to-right input arrival is proposed. Making full use of the delay of the input arrival, it produces the sum within a small constant delay after the arrival of the final bits. Its amount of hardware is proportional to the operand length. It can be applied to the quotient conversion in an array divider.

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Index Terms:
Arithmetic circuit, adder, on-the-fly conversion, divider.
Citation:
Naofumi Takagi, Takashi Horiyama, "A High-Speed Reduced-Size Adder Under Left-to-Right Input Arrival," IEEE Transactions on Computers, vol. 48, no. 1, pp. 76-80, Jan. 1999, doi:10.1109/12.743413
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