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Multiplexer-Based Array Multipliers
January 1999 (vol. 48 no. 1)
pp. 15-23

Abstract—A new algorithm for the multiplication of two n-bit numbers based on the synchronous computation of the partial sums of the two operands is presented. The proposed algorithm permits an efficient realization of the parallel multiplication using iterative arrays. At the same time, it permits high-speed operation. Multiplier arrays for positive numbers and numbers in two's complement form based on the proposed technique are implemented. Also, an efficient pipeline form of the proposed multiplication scheme is introduced. All multipliers obtained have low circuit complexity permitting high-speed operation and the interconnections of the cells are regular, well-suited for VLSI realization.

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Index Terms:
Array multipliers, multiplication algorithm, two's complement multiplication, pipeline multipliers.
Citation:
Kiamal Z. Pekmestzi, "Multiplexer-Based Array Multipliers," IEEE Transactions on Computers, vol. 48, no. 1, pp. 15-23, Jan. 1999, doi:10.1109/12.743408
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