This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Low-Power Divider
January 1999 (vol. 48 no. 1)
pp. 2-14

Abstract—The general objective of our work is to develop methods to reduce the energy consumption of arithmetic modules while maintaining the delay unchanged and keeping the increase in the area to a minimum. Here, we illustrate some techniques for dividers realized in CMOS technology. The energy dissipation reduction is carried out at different levels of abstraction: from the algorithm level down to the implementation, or gate, level. We describe the use of techniques such as switching-off not active blocks, retiming, dual voltage, and equalizing the paths to reduce glitches. Also, we describe modifications in the on-the-fly conversion and rounding algorithm and in the redundant representation of the residual in order to reduce the energy dissipation. The techniques and modifications mentioned above are applied to a radix-4 divider, realized with static CMOS standard cells, for which a reduction of 40 percent is obtained with respect to the standard implementation. This reduction is expected to be about 60 percent if low-voltage gates, for dual voltage implementation, are available. The techniques used here should be applicable to a variety of arithmetic modules which have similar characteristics.

[1] J.A. Prabhu and G.B. Zyner, "167 MHz Radix-8 Divide and Squareroot Using Overlapped Radix-2 Stages," Proc. 12th Symp. Computer Arithmetic, IEEE CS Press, 1995, pp. 155-162.
[2] N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley, 1994.
[3] A.P. Chandrakasan and R.W. Brodersen, "Low Power Digital CMOS Design," Kluwer Academic Pub., Boston, Mass., 1995.
[4] J.M. Rabaey et al., Low Power Design Methodologies. Kluwer Academic, 1996.
[5] M.D. Ercegovac and T. Lang, Division and Square Root—Digit-Recurrence Algorithms and Implementations. Kluwer Academic, 1994.
[6] Compass Design Automation, Passport−0.6-Micron, 3-Volt, High-Performance Standard Cell Library. Compass Design Automation, Inc., 1994.
[7] A. Nannarelli, "PET: Power Evaluation Tool," http://www.eng.uci.edu/numlabPET/, Aug. 1996.
[8] A. Nannarelli and T. Lang, "Low-Power Radix-8 Divider," Proc. Int'l Conf. Computer Design, pp. 420-426, Oct. 1998.
[9] I. Koren, Computer Arithmetic Algorithms.Englewood Cliffs, N.J.: Prentice Hall, 1993.
[10] J. Monteiro, S. Devadas, and A. Ghosh, "Retiming Sequential Circuits for Low Power," Proc. 1993 Int'l Conf. Computer-Aided Design (ICCAD), pp. 398-402, Nov. 1993.
[11] K. Usami and M. Horowitz, "Clustered Voltage Scaling Technique for Low-Power Design," Int'l Symp. Low-Power Design, ACM Press, New York, 1995, pp. 3-8.
[12] T. Lang, E. Musol, and J. Cortadella, “Individual Flip-Flops with Gated Clocks for Low Power Datapaths,” IEEE Trans. Circuits and System-II: Analog and Digital Signal Processing, vol. 44, no. 6, June 1997.

Index Terms:
Floating-point division, digit-recurrence division, low-power.
Citation:
Alberto Nannarelli, Tomás Lang, "Low-Power Divider," IEEE Transactions on Computers, vol. 48, no. 1, pp. 2-14, Jan. 1999, doi:10.1109/12.743407
Usage of this product signifies your acceptance of the Terms of Use.