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Low-Power Divider
January 1999 (vol. 48 no. 1)
pp. 2-14

Abstract—The general objective of our work is to develop methods to reduce the energy consumption of arithmetic modules while maintaining the delay unchanged and keeping the increase in the area to a minimum. Here, we illustrate some techniques for dividers realized in CMOS technology. The energy dissipation reduction is carried out at different levels of abstraction: from the algorithm level down to the implementation, or gate, level. We describe the use of techniques such as switching-off not active blocks, retiming, dual voltage, and equalizing the paths to reduce glitches. Also, we describe modifications in the on-the-fly conversion and rounding algorithm and in the redundant representation of the residual in order to reduce the energy dissipation. The techniques and modifications mentioned above are applied to a radix-4 divider, realized with static CMOS standard cells, for which a reduction of 40 percent is obtained with respect to the standard implementation. This reduction is expected to be about 60 percent if low-voltage gates, for dual voltage implementation, are available. The techniques used here should be applicable to a variety of arithmetic modules which have similar characteristics.

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Index Terms:
Floating-point division, digit-recurrence division, low-power.
Alberto Nannarelli, Tomás Lang, "Low-Power Divider," IEEE Transactions on Computers, vol. 48, no. 1, pp. 2-14, Jan. 1999, doi:10.1109/12.743407
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