Publication 1998 Issue No. 11 - November Abstract - Asynchronous Parallel Prefix Computation
Asynchronous Parallel Prefix Computation
November 1998 (vol. 47 no. 11)
pp. 1244-1252
 ASCII Text x Rajit Manohar, José A. Tierno, "Asynchronous Parallel Prefix Computation," IEEE Transactions on Computers, vol. 47, no. 11, pp. 1244-1252, November, 1998.
 BibTex x @article{ 10.1109/12.736437,author = {Rajit Manohar and José A. Tierno},title = {Asynchronous Parallel Prefix Computation},journal ={IEEE Transactions on Computers},volume = {47},number = {11},issn = {0018-9340},year = {1998},pages = {1244-1252},doi = {http://doi.ieeecomputersociety.org/10.1109/12.736437},publisher = {IEEE Computer Society},address = {Los Alamitos, CA, USA},}
 RefWorks Procite/RefMan/Endnote x TY - JOURJO - IEEE Transactions on ComputersTI - Asynchronous Parallel Prefix ComputationIS - 11SN - 0018-9340SP1244EP1252EPD - 1244-1252A1 - Rajit Manohar, A1 - José A. Tierno, PY - 1998KW - Asynchronous circuitsKW - binary additionKW - prefix computationKW - average-case latency.VL - 47JA - IEEE Transactions on ComputersER -

Abstract—The prefix problem is to compute all the products $x_1 \otimes x_2 \otimes \cdots \otimes x_k,$ for 1 ≤kn, where $\otimes$ is an associative binary operation. We start with an asynchronous circuit to solve this problem with O(log n) latency and O(n log n) circuit size, with $O(n)\ \otimes\!\!-{\rm operations}$ in the circuit. Our contributions are: 1) a modification to the circuit that improves its average-case latency from O(log n) to O(log log n) time, and 2) a further modification that allows the circuit to run at full-throughput, i.e., with constant response time. The construction can be used to obtain a asynchronous adder with O(log n) worst-case latency and O(log log n) average-case latency.

[1] A.W. Burks, H.H. Goldstein, and J. von Neumann, "Preliminary Discussion of the Logical Design of an Electronic Computing Instrument," Inst. for Advanced Study, Princeton, N.J., June 1946. Also available in Collected Works of John von Neumann, vol. 5, A.H. Taub, ed., pp. 34-79. New York: Macmillan, 1963.
[2] J.D. Garside, "A CMOS VLSI Implementation of an Asynchronous ALU," Proc. IFIP Workshop Asynchronous Design Methodologies,Manchester, U.K., 1993.
[3] P. Gemmell and M. Harchol, "Tight Bounds on Expected Time to Add Correctly and Add Mostly Correctly," Information Processing Letters, vol. 49, pp. 77-83, 1994.
[4] C.A.R. Hoare,“Communicating sequential processes,” Comm. of the ACM, vol. 21, no. 8, pp. 666-677, Aug. 1978.
[5] D.J. Kinniment, "An Evaluation of Asynchronous Addition," IEEE Trans. VLSI Systems, vol. 4, no. 1, pp. 137-140, Mar. 1996.
[6] R.E. Ladner and M.J. Fischer, "Parallel Prefix Computation," J. ACM, vol. 27, no. 4, pp. 831-838, Oct. 1980.
[7] F.T. Leighton,Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes.San Mateo, Calif.: Morgan Kaufmann, 1992.
[8] A.J. Martin, "Compiling Communicating Processes into Delay-Insensitive VLSI Circuits," Distributed Computing, vol. 1, no. 4, 1986.
[9] A.J. Martin, "Asynchronous Datapaths and the Design of an Asynchronous Adder," Formal Methods in Systems Design, vol. 1, no. 1, pp. 119-139, 1992.
[10] S. Winograd, "On the Time Required to Perform Addition," J. ACM, vol. 12, no. 2, pp. 277-285, Apr. 1965.

Index Terms:
Asynchronous circuits, binary addition, prefix computation, average-case latency.
Citation:
Rajit Manohar, José A. Tierno, "Asynchronous Parallel Prefix Computation," IEEE Transactions on Computers, vol. 47, no. 11, pp. 1244-1252, Nov. 1998, doi:10.1109/12.736437