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New Low-Complexity Bit-Parallel Finite Field Multipliers Using Weakly Dual Bases
November 1998 (vol. 47 no. 11)
pp. 1223-1234

Abstract—New structures of bit-parallel weakly dual basis (WDB) multipliers over the binary ground field are proposed. An upper bound on the size complexity of bit-parallel multiplier using an arbitrary generating polynomial is given. When the generating polynomial is an irreducible trinomial xm + xk + 1, $1\le k\le \left\lfloor {{{m \over 2}}} \right\rfloor,$ the structure of the proposed bit-parallel multiplier requires only m2 two-input AND gates and at most m2$-$1 XOR gates. The time delay is no greater than $T_A + (\lceil \log_2 m\rceil + 2)T_X,$ where TA and TX are the time delays of an AND gate and an XOR gate, respectively.

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Index Terms:
Bit-parallel multiplier, finite field arithmetic, irreducible polynomials, trinomials, weakly dual basis.
Huapeng Wu, M. Anwarul Hasan, Ian F. Blake, "New Low-Complexity Bit-Parallel Finite Field Multipliers Using Weakly Dual Bases," IEEE Transactions on Computers, vol. 47, no. 11, pp. 1223-1234, Nov. 1998, doi:10.1109/12.736433
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