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Test Data Decompression for Multiple Scan Designs with Boundary Scan
November 1998 (vol. 47 no. 11)
pp. 1188-1200

Abstract—The paper presents an efficient scheme to compress and decompress in parallel deterministic test patterns for circuits with multiple scan chains. It employs a boundary-scan-based environment for high quality testing with flexible trade-offs between test data volume and test application time while achieving a complete fault coverage for any fault model for which test cubes are obtainable. It also reduces bandwidth requirements, as all test cube transfers involve compressed data. The test patterns are generated by the reseeding of a two-dimensional hardware structure which is comprised of a linear feedback shift register (LFSR), a network of exclusive-or (XOR) gates used to scramble the bits of test vectors, and extra feedbacks which allow including internal scan flip-flops into the decompressor structure to minimize the area overhead. The test data decompressor operates in two modes: pseudorandom and deterministic. In the first mode, the pseudorandom pattern generator (PRPG) is used purely as a generator of test vectors. In the latter case, variable-length seeds are serially scanned through the boundary-scan interface into the PRPG and parts of internal scan chains and, subsequently, a decompression is performed in parallel by means of the PRPG and selected scan flip-flops interconnected to form the decompression device. Extensive experiments with the largest ISCAS' 89 benchmarks show that the proposed technique greatly reduces the amount of test data in a cost effective manner.

[1] V.D. Agrawal, C.R. Kime, and K.K. Saluja, A Tutorial on Built-In Self-Test, Part 1: Principles IEEE Design and Test of Computers, pp. 73-82, Mar. 1993.
[2] V.D. Agrawal, C.R. Kime, and K.K. Saluja, A Tutorial on Built-In Self-Test, Part 2: Applications IEEE Design and Test of Computers, pp. 69-77, June 1993.
[3] S. Akers and W. Jansz, Test Set Embedding in a BIST Environment Proc. Int'l Test Conf., pp. 257-263, 1989.
[4] P.H. Bardell, W.H. McAnney, and J. Savir, Built-In Test for VLSI, John Wiley&Sons, New York, 1987.
[5] Z. Barsilai, D. Coppersmith, and A.L. Rosenberg, "Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing," IEEE Trans. Computers, vol. 32, no. 2, pp. 190-194, Feb. 1983.
[6] R. Dandapani, J.H. Patel, and J.A. Abraham, "Design of Test Pattern Generators for Built-In Test," Proc. Int'l Test Conf., pp. 315-319, 1984.
[7] W. Daehn and J. Mucha, "Hardware Test Pattern Generators for Built-In Test," Proc. Int'l Test Conf., pp. 110-113, 1981.
[8] C. Dufaza and G. Gambon, "LFSR-Based Deterministic and Pseudo-Random Test Patterns Generators Structures," Proc. European Test Conf., pp. 27-34, 1991.
[9] S. Hellebrand et al., "Built-in Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers," IEEE Trans. Computers, vol. 44, no. 2, Feb. 1995, pp. 223-233.
[10] S. Hellebrand, B. Reeb, S. Tarnick, and H.-J. Wunderlich, "Pattern Generation for a Deterministic BIST Scheme," Proc. Int'l Conf. Computer-Aided Design, pp. 88-94, 1995.
[11] S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, "Generation of Vector Patterns Through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers," Proc. IEEE Int'l Test Conf., pp. 120-129, 1992.
[12] W.J. Hurd, "Efficient Generation of Statistically Good Pseudonoise by Linearly Interconnected Shift Registers," IEEE Trans. Computers, vol. 23, no. 2, pp. 146-152, Feb. 1974.
[13] B. Koenemann, "LFSR-Coded Test Patterns for Scan Designs" Proc. European Test Conf., pp. 237-242, 1991.
[14] C.M. Maunder and R.E. Tulloss, The Test Access Port and Boundary-Scan Architecture. IEEE CS Press, 1990.
[15] J. Rajski and J. Tyszer, "On Linear Dependencies in Subspaces of LFSR-Generated Sequences," IEEE Trans. Computers, vol. 45, no. 10, Oct. 1996, pp. 1212-1216.
[16] J. Rajski and J. Tyszer, "A Parallel Decompressor and Related Methods and Apparatuses," U.S. patent application, 1996.
[17] B.H. Seiss, P.M. Trousborst, and M.H. Schulz, "Test Point Insertion for Scan-Based BIST," Proc. European Test Conf., pp. 253-262, 1991.
[18] N. Tamarapalli and J. Rajski, "Constructive Multi-Phase Test Point Insertion for Scan-Based BIST," Proc. Int'l Test Conf., pp. 649-658, 1996.
[19] L.T. Wang and E.J. McCluskey, "Circuits for Pseudo-Exhaustive Test Pattern Generation," Proc. Int'l Test Conf., pp. 25-37, 1986.
[20] H.-J. Wunderlich and S. Hellebrand, "The Pseudo-Exhaustive Test of Sequential Circuits," IEEE Trans. Computer-Aided Design, vol. 11, no. 1, pp. 26-33, 1992.
[21] S. Venkataraman et al., A Efficient BIST Scheme Based on Reseeding of Multiple Polynomial LFSRs Proc. Int'l Conf. Computer-Aided Design (ICCAD), 1993.
[22] N. Zacharia, J. Rajski, and J. Tyszer, "Decompression of Test Data Using Variable-Length Seed LFSRs," Proc. VLSI Test Symp., pp. 426-433, 1995.
[23] N. Zacharia, J. Rajski, J. Tyszer, and J.A. Waicukauski, "Two-Dimensional Test Data Decompressor for Multiple Scan Designs," Proc. Int'l Test Conf., pp. 186-194, 1996.

Index Terms:
Boundary scan, built-in self-test, design for testability, reseeding of LFSRs, multiple scan chains, scan-based designs, test data decompression.
Citation:
Janusz Rajski, Jerzy Tyszer, Nadime Zacharia, "Test Data Decompression for Multiple Scan Designs with Boundary Scan," IEEE Transactions on Computers, vol. 47, no. 11, pp. 1188-1200, Nov. 1998, doi:10.1109/12.736428
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