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Issue No.11 - November (1998 vol.47)
pp: 1171-1187
ABSTRACT
<p><b>Abstract</b>—Many built-in self-testing (BIST) schemes compress the test responses from a <it>k</it>-output circuit to <it>q</it> signature streams, where <it>q</it> << <it>k</it>, a process termed space compaction. The effectiveness of such a compaction method can be measured by its compaction ratio <it>c</it> = <it>k/q</it>. A high compaction ratio can introduce aliasing, which occurs when a faulty test response maps to the fault-free signature. We investigate the problem of designing zero-aliasing space compaction circuits with maximum compaction ratio <it>c</it><sub><it>max</it></sub>. We introduce a graph representation of test responses to study the space compaction process and relate space compactor design to a graph coloring problem. Given a circuit under test, a fault model, and a test set, we determine <it>q</it><sub><it>min</it></sub>, which yields <it>c</it><sub><it>max</it></sub> = <it>k/q</it><sub><it>min</it></sub>. This provides a fundamental bound on the cost of signature-based BIST. We show that <it>q</it><sub><it>min</it></sub>≤ 2 for all the ISCAS 85 benchmark circuits. We develop a systematic design procedure for the synthesis of space compaction circuits and apply it to a number of ISCAS 85 circuits. Finally, we describe multistep compaction, which allows zero aliasing to be achieved with any <it>q</it>, even when <it>q</it><sub><it>min</it></sub> > 1.</p>
INDEX TERMS
Aliasing, built-in self-testing, fault coverage, graph coloring, multistep compaction.
CITATION
Krishnendu Chakrabarty, Brian T. Murray, John P. Hayes, "Optimal Zero-Aliasing Space Compaction of Test Responses", IEEE Transactions on Computers, vol.47, no. 11, pp. 1171-1187, November 1998, doi:10.1109/12.736427
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