
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
Krishnendu Chakrabarty, Brian T. Murray, John P. Hayes, "Optimal ZeroAliasing Space Compaction of Test Responses," IEEE Transactions on Computers, vol. 47, no. 11, pp. 11711187, November, 1998.  
BibTex  x  
@article{ 10.1109/12.736427, author = {Krishnendu Chakrabarty and Brian T. Murray and John P. Hayes}, title = {Optimal ZeroAliasing Space Compaction of Test Responses}, journal ={IEEE Transactions on Computers}, volume = {47}, number = {11}, issn = {00189340}, year = {1998}, pages = {11711187}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.736427}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Optimal ZeroAliasing Space Compaction of Test Responses IS  11 SN  00189340 SP1171 EP1187 EPD  11711187 A1  Krishnendu Chakrabarty, A1  Brian T. Murray, A1  John P. Hayes, PY  1998 KW  Aliasing KW  builtin selftesting KW  fault coverage KW  graph coloring KW  multistep compaction. VL  47 JA  IEEE Transactions on Computers ER   
Abstract—Many builtin selftesting (BIST) schemes compress the test responses from a
[1] B.T. Murray and J.P. Hayes, "Testing ICs: Getting to the Core of the Problem," Computer, pp. 3238, Nov. 1996.
[2] F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Simulator in Fortran," Proc. 1985 Int'l Symp. Circuits and Systems, pp. 695698, 1985.
[3] "Cabri: A Tool for Research and Teaching in Graph Theory," Laboratoire de Structures Discrètes et de Didactique, IMAG, Grenoble, France, Dec. 1993.
[4] K. Chakrabarty and J.P. Hayes, "AliasingFree Error Detection (ALFRED)," Proc. 1993 VLSI Test Symp., pp. 260267, Apr. 1993.
[5] K. Chakrabarty and J.P. Hayes, "Test Response Compaction Using Multiplexed Parity Trees," IEEE Trans. ComputerAided Design, vol. 15, pp. 1,3991,408, Nov. 1996.
[6] K. Chakrabarty, "ZeroAliasing Space Compaction Using Linear Compactors with Bounded Overhead," IEEE Trans. ComputerAided Design, vol. 17, pp. 452457, May 1998.
[7] S.R. Das et al., "An Improved Output Compaction Technique for BuiltIn Self Test in VLSI Circuits," Proc. 1995 Int'l Conf. VLSI, pp. 403407, 1995.
[8] H. Fujiwara and A. Yamamoto, Parity Scan Design to Reduce the Cost of Test Application IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 12, no. 10, pp. 16041611, 1993.
[9] M.C. Hansen and J.P. Hayes, "HighLevel Test Generation Using PhysicallyInduced Faults," Proc. 1995 VLSI Test Symp., pp. 2028, 1995.
[10] F. Harary, Graph Theory.Reading, Mass.: AddisonWesley, 1969.
[11] W.B. Jone and S.R. Das, "Space Compression Method for BuiltIn Self Testing of VLSI Circuits," Int'l J. ComputerAided Design, vol. 3, pp. 309322, Sept. 1991.
[12] M. Karpovsky and P. Nagvajara, "Optimal Time and Space Compression of Test Responses for VLSI Devices," Proc. 1987 Int'l Test Conf., pp. 946955, 1987.
[13] H.K. Lee and D.S. Ha, "An Efficient Forward Fault Simulation Algorithm Based on the Parallel Pattern Single Fault Propagation," Proc. 1991 Int'l Test Conf., pp. 946955, 1991.
[14] H.K. Lee and D.S. Ha, "On the Generation of Test Patterns for Combinational Circuits," Technical Report No. 1293, Dept. of Electrical Eng., Virginia Polytechnic Inst. and State Univ., Dec. 1993.
[15] M. Lempel and S.K. Gupta, "ZeroAliasing for Modeled Faults," IEEE Trans. Computers, vol. 44, no. 11, pp. 1,2831,295, Nov. 1995.
[16] Y.K. Li and J.P. Robinson, "Space Compaction Methods with Output Data Modification," IEEE Trans. ComputerAided Design, vol. 6, pp. 290294, Mar. 1987.
[17] E. Masson, "A Structural Study and Algorithms in Vertex Coloring," PhD thesis, Dept. of Electrical Eng., McGill Univ., Jan. 1996.
[18] M. Irani, B. Rousso, and S. Peleg, “Image Sequence Enhancement Using Multiple Motions Analysis,” Proc. 1992 Conf. Computer Vision and Pattern Recognition, pp. 216221, 1992.
[19] I. Pomeranz, S.M. Reddy, and R. Tangirala, "On Achieving Zero Aliasing for Modeled Faults," Proc. 1992 European Design Automation Conf., pp. 291299, Mar. 1992.
[20] I. Pomeranz, L.N. Reddy, and S.M. Reddy, "COMPACTEST: A Method to Generate Compact Test Sets for Combinational Circuits," Proc. 1991 Int'l Test Conf., pp. 194203, Oct. 1991.
[21] B. Pouya and N.A. Touba, "Synthesis of ZeroAliasing ElementaryTree Space Compactors," Proc. 1998 VLSI Test Conf., pp. 7077, 1998.
[22] D.K. Pradhan and S. Gupta, A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression IEEE Trans. Computers, vol. 40, no. 6, June 1991.
[23] S.M. Reddy, K.K. Saluja, and M.G. Karpovsky, "A Data Compression Technique for BuiltIn SelfTest," IEEE Trans. Computers, vol. 37, no. 9, pp. 1,1511,156, Sept. 1988.
[24] J. Savir, "Shrinking Wide Compressors," IEEE Trans. ComputerAided Design, vol. 14, pp. 1,3791,387, Nov. 1995.
[25] A. Ivanov, B. Tsuji, and Y. Zorian, "Programmable BIST Space Compactors," IEEE Trans. Computers, vol. 45, no. 12, pp. 1,3931,404, Dec. 1996.
[26] Texas Instruments, The TTL Data Book, vol. 2. Dallas, Tex., 1988.
[27] Y. Zorian and A. Ivanov, "Programmable Space Compaction for BIST," Proc. 1993 Int'l Symp. FaultTolerant Computing, pp. 340349, 1993.