Publication 1998 Issue No. 10 - October Abstract - Systolic Array Implementation of Euclid's Algorithm for Inversion and Division in GF (2m)
Systolic Array Implementation of Euclid's Algorithm for Inversion and Division in GF (2m)
October 1998 (vol. 47 no. 10)
pp. 1161-1167
 ASCII Text x Jyh-Huei Guo, Chin-Liang Wang, "Systolic Array Implementation of Euclid's Algorithm for Inversion and Division in GF (2m)," IEEE Transactions on Computers, vol. 47, no. 10, pp. 1161-1167, October, 1998.
 BibTex x @article{ 10.1109/12.729800,author = {Jyh-Huei Guo and Chin-Liang Wang},title = {Systolic Array Implementation of Euclid's Algorithm for Inversion and Division in GF (2m)},journal ={IEEE Transactions on Computers},volume = {47},number = {10},issn = {0018-9340},year = {1998},pages = {1161-1167},doi = {http://doi.ieeecomputersociety.org/10.1109/12.729800},publisher = {IEEE Computer Society},address = {Los Alamitos, CA, USA},}
 RefWorks Procite/RefMan/Endnote x TY - JOURJO - IEEE Transactions on ComputersTI - Systolic Array Implementation of Euclid's Algorithm for Inversion and Division in GF (2m)IS - 10SN - 0018-9340SP1161EP1167EPD - 1161-1167A1 - Jyh-Huei Guo, A1 - Chin-Liang Wang, PY - 1998KW - Finite field divisionKW - finite field inversionKW - parallel-in parallel-out architectureKW - serial-in serial-out architectureKW - standard basisKW - systolic arrayKW - VLSI.VL - 47JA - IEEE Transactions on ComputersER -

Abstract—This paper presents two new systolic arrays to realize Euclid's algorithm for computing inverses and divisions in finite fields GF(2m) with the standard basis representation. One of these two schemes is parallel-in parallel-out, and the other is serial-in serial-out. The former employs O(m2) area complexity to provide the maximum throughput in the sense of producing one result every clock cycle, while the latter achieves a throughput of one result per m clock cycles using O(m· log2m) area complexity. Both of the proposed architectures are highly regular and, thus, well suited to VLSI implementation. As compared to existing related systolic architectures with the same throughput performance, the proposed parallel-in parallel-out scheme reduces the hardware complexity (and, thus, the area-time product) by a factor of O(m) and the proposed serial-in serial-out scheme by a factor of O(m/log2m).

[1] W.W. Peterson and E.J. Weldon Jr., Error-Correcting Codes.Cambridge, Mass.: MIT Press, 1972.
[2] R.E. Blahut, Theory and Practice of Error Control Codes.Reading, Mass.: Addsion-Wesley, 1983.
[3] W. Diffie and M.E. Hellman, New Directions in Cryptography IEEE Trans. Information Theory, vol. 22, pp. 644-654, 1976.
[4] G.B. Agnew, R.C. Mullin, I.M. Onyszchuk, and S.A. Vanstone, "An Implementation for a Public-Key Cryptosystems," J. Cryptology, vol. 3, pp. 63-79, 1991.
[5] D. Bini and V.Y. Pan, Polynomial and Matrix Computations, vol. 1, Fundamental Algorithms.Boston: Birkhäuser, 1994.
[6] C.C. Wang,T.K. Truong,H.M. Shao,L.J. Deutsch,J.K. Omura, and I.S. Reed,"VLSI Architectures for Computing Multiplications and Inverses inGF(2m)," IEEE Trans. Computers, vol. 34, no. 8, pp. 709-716, Aug. 1985.
[7] G-L. Feng,"A VLSI Architecture for Fast Iinversion inGF(2m)," IEEE Trans. Computers, vol. 38, no. 10, pp. 1,383-1,386, Oct. 1989.
[8] K. Araki, I. Fujita, and M. Morisue, "Fast Inverters Over Finite Field Based on Euclid's Algorithm," Trans. Inst. Electronics, Information, and Comm. Eng., Section E, English, vol. E-72, pp. 1,230-1,234, Nov. 1989.
[9] H. Brunner, A. Curiger, and M. Hofstetter, On Computing Multiplicative Inverses in${\rm GF}(2^m)$ IEEE Trans. Computers, vol. 42, no. 8, pp. 1010-1015, Aug. 1993.
[10] S.-W. Wei, VLSI Architectures for Computing Exponentiations, Multiplicative Inverses, and Divisions in${\rm GF}(2^m)$ Proc. Int'l Symp. Circuits and Systems (ISCAS '94), pp. 203-206, 1994.
[11] C.-L. Wang and J.-H. Guo, "New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m)," Proc. 1995 European Conf. Circuit Theory Design, pp. 431-434,Istanbul, Turkey, Aug. 1995.
[12] C.L. Wang and J.L. Lin, A Systolic Architecture for Computing Inverses and Divisions in Finite Fields${\rm GF}(2^m)$ IEEE Trans. Computers, vol. 42, no. 9, pp. 1141-1146, Sept. 1993.
[13] M.A. Hasan and V.K. Bhargava,"Bit-Serial Systolic Divider and Multiplier for Finite FieldsGF(2m)," IEEE Trans. Computers, vol. 41, no. 8, pp. 972-980, Aug. 1992.
[14] S.T.J. Fenn, M. Benaissa, and D. Taylor, $GF(2^m)$Multiplication and Division over the Dual Basis IEEE Trans. Computers, vol. 45, no. 3, pp. 319-327, Mar. 1996.
[15] H.T. Kung, "Why Systolic Architectures?," Computer, vol. 15, no. 1, pp. 37-46, Jan. 1982.
[16] S.Y. Kung, VLSI Array Processors. Prentice Hall, 1988.

Index Terms:
Finite field division, finite field inversion, parallel-in parallel-out architecture, serial-in serial-out architecture, standard basis, systolic array, VLSI.
Citation:
Jyh-Huei Guo, Chin-Liang Wang, "Systolic Array Implementation of Euclid's Algorithm for Inversion and Division in GF (2m)," IEEE Transactions on Computers, vol. 47, no. 10, pp. 1161-1167, Oct. 1998, doi:10.1109/12.729800