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IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays
October 1998 (vol. 47 no. 10)
pp. 1136-1152
ASCII Text
x 
 
Lan Zhao, Duncan M. Hank Walker, Fabrizio Lombardi, "IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays," IEEE Transactions on Computers, vol. 47, no. 10, pp. 1136-1152, October, 1998.
 
 
BibTex
x
 
@article{ 10.1109/12.729796,
author = {Lan Zhao and Duncan M. Hank Walker and Fabrizio Lombardi},
title = {IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays},
journal ={IEEE Transactions on Computers},
volume = {47},
number = {10},
issn = {0018-9340},
year = {1998},
pages = {1136-1152},
doi = {http://doi.ieeecomputersociety.org/10.1109/12.729796},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays
IS - 10
SN - 0018-9340
SP1136
EP1152
EPD - 1136-1152
A1 - Lan Zhao,
A1 - Duncan M. Hank Walker,
A1 - Fabrizio Lombardi,
PY - 1998
KW - Testing
KW - FPGA
KW - bridging fault
KW - IDDQ test
KW - configurable logic blocks
KW - programming phase.
VL - 47
JA - IEEE Transactions on Computers
ER -
 

Abstract—This paper presents an IDDQ-based test strategy for detecting bridging faults in the logic resources of reprogrammable Field Programmable Gate Arrays (FPGAs). The proposed approach utilizes the programmability of the Configurable Logic Blocks (CLBs) to achieve 100 percent coverage of IDDQ-testable bridging faults. We use a hieararchical approach for generating tests and configurations. At the chip level, the CLBs are viewed as a homogeneous two-dimensional array. Two configuration strategies are suggested to simultaneously test each CLB. Within each CLB, we test for external bridging faults between the combinational and sequential logic modules (e.g., flip-flops, multiplexers, lookup tables). Finally, we test for internal bridging faults within each module based on their implementation. Since reconfiguration programming time dominates total test time, even with slow IDDQ vectors, we use a bottom-up test generation approach to minimize the number of programming phases first and, then, to minimize the number of test vectors. The Xilinx XC4000 family of SRAM-based FPGAs is used as an example application of the proposed approach. One hundred percent coverage for IDDQ-testable bridging faults is achieved in five programming phases and 16 IDDQ vectors. Since the lookup tables in the CLB can be configured as RAM, the RAM modes are also tested. This requires a further phase, using 48 test vectors and 38 IDDQ measurements.

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Index Terms:
Testing, FPGA, bridging fault, IDDQ test, configurable logic blocks, programming phase.
Citation:
Lan Zhao, Duncan M. Hank Walker, Fabrizio Lombardi, "IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays," IEEE Transactions on Computers, vol. 47, no. 10, pp. 1136-1152, Oct. 1998, doi:10.1109/12.729796
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