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| Dhananjay S. Phatak, "Comments on Duprat and Muller's Branching CORDIC Paper," IEEE Transactions on Computers, vol. 47, no. 9, pp. 1037-1040, September, 1998. | |||
| BibTex | x | ||
| @article{ 10.1109/12.713326, author = {Dhananjay S. Phatak}, title = {Comments on Duprat and Muller's Branching CORDIC Paper}, journal ={IEEE Transactions on Computers}, volume = {47}, number = {9}, issn = {0018-9340}, year = {1998}, pages = {1037-1040}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.713326}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Comments on Duprat and Muller's Branching CORDIC Paper IS - 9 SN - 0018-9340 SP1037 EP1040 EPD - 1037-1040 A1 - Dhananjay S. Phatak, PY - 1998 KW - Branching CORDIC KW - constant scale factor KW - signed-digit representation KW - corrections KW - errata. VL - 47 JA - IEEE Transactions on Computers ER - | |||
Abstract—In [1], Duprat and Muller introduced the ingenious "Branching CORDIC" algorithm. It enables a fast implementation of CORDIC algorithm using signed digits and requires a constant normalization factor. This correspondence corrects some errors in the original paper. All the page numbers quoted are from [1].
[1] J. Duprat and J.-M Muller,"The CORDIC Algorithm: New Results for Fast VLSI Implemenation," IEEE Trans. Computers, vol. 42, no. 2, pp. 168-178 Feb. 1993.
[2] I. Koren, Computer Arithmetic Algorithms.Englewood Cliffs, N.J.: Prentice Hall, 1993.
[3] B. Parhami, "Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations," IEEE Trans. Computers, vol. 39, no. 1, pp. 89-98, Jan. 1990.
[4] D.S. Phatak and I. Koren, "Hybrid Signed-Digit Number Systems: A Unified Framework for Redundant Number Representations with Bounded Carry Propagation Chains," IEEE Trans. Computers, special issue on computer arithmetic, vol. 43, no. 8, pp. 880-891, Aug. 1994. (An unabridged version is available on the web at.)
[5] N. Takagi,T. Asada, and S. Yajima,"Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation," IEEE Trans. Computers, vol. 40, no. 9, pp. 989-995, Sept. 1991.
[6] D.S. Phatak, "Double Step Branching CORDIC: A New Algorithm for Fast Sine and Cosine Generation," IEEE Trans. Computers, vol. 47, no. 5, pp. 587-602, May 1998.
[7] Y. Harata, Y. Nakamura, H. Nagese, M. Takigawa, and N. Takagi, "A High-Speed Multiplier Using a Redundant Binary Adder Tree," IEEE J. Solid-State Circuits, vol. 22, pp. 28-34, Feb. 1987.
[8] J.M. Muller, Elementary Functions. Algorithms and Implementation. Birkhauser, 1997.