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Zeljko Zilic, Zvonko G. Vranesic, "Using Decision Diagrams to Design ULMs for FPGAs," IEEE Transactions on Computers, vol. 47, no. 9, pp. 971982, September, 1998.  
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@article{ 10.1109/12.713316, author = {Zeljko Zilic and Zvonko G. Vranesic}, title = {Using Decision Diagrams to Design ULMs for FPGAs}, journal ={IEEE Transactions on Computers}, volume = {47}, number = {9}, issn = {00189340}, year = {1998}, pages = {971982}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.713316}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  Using Decision Diagrams to Design ULMs for FPGAs IS  9 SN  00189340 SP971 EP982 EPD  971982 A1  Zeljko Zilic, A1  Zvonko G. Vranesic, PY  1998 KW  FPGAs KW  ULMs KW  BDDs KW  classification of logic functions KW  synthesis of logic functions. VL  47 JA  IEEE Transactions on Computers ER   
Abstract—Many modern Field Programmable Logic Arrays (FPGAs) use lookup table (LUT) logic blocks which can be programmed to realize any function of a fixed number of inputs. It is possible to employ logic blocks that realize only a subset of all functions, while the rest can be obtained by permuting and negating the inputs. Such blocks, known as Universal Logic Modules (ULMs), have already been considered for application in FPGAs; in this paper, we propose a new class of ULMs which is more useful in the FPGA environment. Methodology for systematic development of such blocks is presented, based on the BDD description of logic functions. We give an explicit construction of a threeinput LUT replacement that requires only five programming bits, which is the optimum for such ULMs. A realistic size fourinput LUT replacement is obtained which uses 13 programming bits.
[1] A. Aggarwal and D. Lewis, "Routing Architectures for Hierarchical FieldProgrammable Gate Arrays," Proc. Custom Integrated Circuits Conf., IEEE, 1994, pp. 475478.
[2] Altera Corp., Data Book.San Jose, Calif., 1995.
[3] Atmel Corp., Configurable Logic Design and Application Book.San Jose, Calif., 1995.
[4] Bell Northern Research, Design Rules for CMC 0.8micron BiCMOS, a Version of BATMOS.Ottawa, Canada, 1993.
[5] V. Betz and J. Rose, "ClusterBased Logic Blocks for FPGAs: AreaEfficiency vs. Input Sharing and Size," Proc. CICC '97,Santa Clara, Calif., pp. 551554, Apr. 1997.
[6] R.E. Bryant, "GraphBased Algorithms for Boolean Function Manipulation," IEEE Trans. Computers, Vol. C35, No. 8, Aug. 1986, pp. 667690.
[7] X. Chen and X. Wu, "Derivation of Universal Logic Modules, for n≥3, by Algebraic Means," IEE Proc., Pt. E, vol. 128, no. 5, pp. 205211, Sept. 1981.
[8] P. Chow, S.O. Seo, J. Rose, K. Chung, I. Rahardja, and G. Paez, "Architecture and CircuitLevel Design of an SRAMBased FieldProgrammable Gate Array," IEEE Trans. VLSI, to appear.
[9] J. Cong and Y.H. Hwang, "Boolean Matching for Complex PLBs in LUTbased FPGAs with Application to Architecture Evaluation," Proc. Int'l Symp. FPGAs, FPGA '98, pp. 2734., Feb. 1998.
[10] J.N. Culliney, M.H. Young, T. Nakagava, and S. Muroga, "Results of the Synthesis of Optimal Networks of AND and OR Gates for FourVariable Switching Functions," IEEE Trans. Computers, vol. 27, no. 1, pp. 7685, Jan. 1979.
[11] R. L. Graham, D. E. Knuth, and O. Patashnik,Concrete Mathematics. Reading, MA: AddisonWesley, 1989.
[12] M. Harrison, "Counting Theorems and their Applications to Classification of Switching Functions," Recent Developments in Switching Theory, A. Mukhopadhyay, ed., pp. 86121. Academic Press, 1971.
[13] J.S.L. Hurst, D.M. Miller,, and J.C. Muzio,Spectral Techniques in Digital Logic. Orlando, Fla.: Academic Press, 1985.
[14] D. Jones and D. Lewis, "A Time Multiplexed FPGA Architecture for Logic Emulation," Proc. Third Int'l Symp. FPGAs, FPGA '95, pp. 121126,Monterey Bay, Calif., Feb. 1995.
[15] C.C. Lin, M. MarekSadowska, and D. Gatlin, "Universal Logic Gate for FPGA Design," Proc. ICCAD '94, pp. 164168,San Jose, Calif., Oct. 1994.
[16] C.C. Lin, M. MarekSadowska, and D. Gatlin, "On Designing Universal Logic Blocks and Their Applications for FPGA Design," IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 27, no. 5, pp. 519527, May 1997.
[17] F.P. Preparata and D.E. Muller, "Generation of NearOptimum Universal Boolean Functions," J. Computer and System Sciences, vol. 4, pp. 93102, Apr. 1970.
[18] J.S. Rose et al., "Architecture of FieldProgrammable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency," IEEE J. SolidState Circuits, Vol. 25, No. 5, Oct. 1990, pp. 12171225.
[19] Representations of Discrete Functions, T. Sasao and M. Fujita, eds. Boston: Kluwer Academic, 1996.
[20] E.M. Sentovich et al., "SIS: A System for Sequential Circuit Synthesis," Memorandum No. UCB/ERL M92/41, Univ. of California Berkeley, May 1992.
[21] H. Stone, "Universal Logic Modules," Recent Developments in Switching Theory, A. Mukhopadhyay, ed., pp. 230254. Academic Press, 1971.
[22] E. Tau, D. Chen, I. Eslick, J. Brown, and A. DeHon, "A First Generation DPGA Implementation," Proc. Third Canadian Workshop Field Programmable Devices, FPD '95, pp. 138143,Montreal, May 1995.
[23] S. Thakur and D.F. Wong, "On Designing ULMBased FPGA Logic Modules," Proc. Third Int'l Symp. FPGAs, pp. 39,Monterey, Calif., Feb. 1995.
[24] S. Thakur and D.F. Wong, "Universal Logic Modules for SeriesParallel Functions," Proc. Fourth Int'l Symp. FPGAs, pp. 3137,Monterey, Calif., Feb. 1996.
[25] C. Tsai and M. MarekSadowska,"Boolean matching using generalized ReedMuller forms," Proc. 31st ACM/IEEE Design Automation Conf., pp. 339344, June 1994.
[26] S. Yang and M.J. Cieselski, "Optimum and Suboptimum Algorithms for Input Encoding and Its Relationship to Logic Minimization," IEEE Trans. ComputerAided Design, vol. 10, no. 1, pp. 412, Jan. 1991.