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Using Decision Diagrams to Design ULMs for FPGAs
September 1998 (vol. 47 no. 9)
pp. 971-982

Abstract—Many modern Field Programmable Logic Arrays (FPGAs) use lookup table (LUT) logic blocks which can be programmed to realize any function of a fixed number of inputs. It is possible to employ logic blocks that realize only a subset of all functions, while the rest can be obtained by permuting and negating the inputs. Such blocks, known as Universal Logic Modules (ULMs), have already been considered for application in FPGAs; in this paper, we propose a new class of ULMs which is more useful in the FPGA environment. Methodology for systematic development of such blocks is presented, based on the BDD description of logic functions. We give an explicit construction of a three-input LUT replacement that requires only five programming bits, which is the optimum for such ULMs. A realistic size four-input LUT replacement is obtained which uses 13 programming bits.

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Index Terms:
FPGAs, ULMs, BDDs, classification of logic functions, synthesis of logic functions.
Citation:
Zeljko Zilic, Zvonko G. Vranesic, "Using Decision Diagrams to Design ULMs for FPGAs," IEEE Transactions on Computers, vol. 47, no. 9, pp. 971-982, Sept. 1998, doi:10.1109/12.713316
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