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Alejandro F. González, Pinaki Mazumder, "MultipleValued SignedDigit Adder Using Negative DifferentialResistance Devices," IEEE Transactions on Computers, vol. 47, no. 9, pp. 947959, September, 1998.  
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@article{ 10.1109/12.713314, author = {Alejandro F. González and Pinaki Mazumder}, title = {MultipleValued SignedDigit Adder Using Negative DifferentialResistance Devices}, journal ={IEEE Transactions on Computers}, volume = {47}, number = {9}, issn = {00189340}, year = {1998}, pages = {947959}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.713314}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  MultipleValued SignedDigit Adder Using Negative DifferentialResistance Devices IS  9 SN  00189340 SP947 EP959 EPD  947959 A1  Alejandro F. González, A1  Pinaki Mazumder, PY  1998 KW  Signeddigit arithmetic KW  multiplevalued logic KW  quantum electronic resonanttunneling circuits. VL  47 JA  IEEE Transactions on Computers ER   
Abstract—This paper describes a new signeddigit full adder (SDFA) circuit consisting of resonanttunneling diodes (RTDs) and metaloxide semiconductor field effect transistors (MOSFETs). The design is primarily based on a multiplevalued logic literal circuit that utilizes the foldedback IV (also known as negative differentialresistance, NDR) characteristics of RTDs to compactly implement its gated transfer function. MOS transistors are configured in
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