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Multiple-Valued Signed-Digit Adder Using Negative Differential-Resistance Devices
September 1998 (vol. 47 no. 9)
pp. 947-959
ASCII Text
x 
 
Alejandro F. González, Pinaki Mazumder, "Multiple-Valued Signed-Digit Adder Using Negative Differential-Resistance Devices," IEEE Transactions on Computers, vol. 47, no. 9, pp. 947-959, September, 1998.
 
 
BibTex
x
 
@article{ 10.1109/12.713314,
author = {Alejandro F. González and Pinaki Mazumder},
title = {Multiple-Valued Signed-Digit Adder Using Negative Differential-Resistance Devices},
journal ={IEEE Transactions on Computers},
volume = {47},
number = {9},
issn = {0018-9340},
year = {1998},
pages = {947-959},
doi = {http://doi.ieeecomputersociety.org/10.1109/12.713314},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Multiple-Valued Signed-Digit Adder Using Negative Differential-Resistance Devices
IS - 9
SN - 0018-9340
SP947
EP959
EPD - 947-959
A1 - Alejandro F. González,
A1 - Pinaki Mazumder,
PY - 1998
KW - Signed-digit arithmetic
KW - multiple-valued logic
KW - quantum electronic resonant-tunneling circuits.
VL - 47
JA - IEEE Transactions on Computers
ER -
 

Abstract—This paper describes a new signed-digit full adder (SDFA) circuit consisting of resonant-tunneling diodes (RTDs) and metal-oxide semiconductor field effect transistors (MOSFETs). The design is primarily based on a multiple-valued logic literal circuit that utilizes the folded-back I-V (also known as negative differential-resistance, NDR) characteristics of RTDs to compactly implement its gated transfer function. MOS transistors are configured in current-mode logic, where addition of two or more digits is achieved by superimposing the signals of individual wires being physically connected at the summing nodes. The proposed SDFA design uses redundant arithmetic representation and, therefore, the circuit can perform addition of two arbitrary size binary numbers in constant time without the need for either carry propagation or carry look-ahead. The SDFA cell design has been verified through simulation by an augmented SPICE simulator that includes new homotopy-based convergence routines to tackle the nonlinear device characteristics of quantum devices. From the simulation result, the SDFA cell has been found to perform addition operation in 3.5 nanoseconds, which is somewhat superior to other multivalued redundant arithmetic circuits reported in the literature. The SDFA cell requires only 13 MOS transistors and one RTD, as opposed to the state-of-the-art CMOS redundant binary adder requiring 56 transistors, and to the conventional multivalued current-mode adder consisting of 34 MOS transistors. In order to verify the simulation result, a prototype SDFA cell has been fabricated using MOSIS 2-micron CMOS process and GaAs-based RTDs connected externally to the MOSFET circuit.

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Index Terms:
Signed-digit arithmetic, multiple-valued logic, quantum electronic resonant-tunneling circuits.
Citation:
Alejandro F. González, Pinaki Mazumder, "Multiple-Valued Signed-Digit Adder Using Negative Differential-Resistance Devices," IEEE Transactions on Computers, vol. 47, no. 9, pp. 947-959, Sept. 1998, doi:10.1109/12.713314
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