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Comparison of Single- and Dual-Pass Multiply-Add Fused Floating-Point Units
September 1998 (vol. 47 no. 9)
pp. 927-937

Abstract—Low power, low cost, and high performance factors dictate the design of many microprocessors targeted to the low-power computing market. The floating-point unit occupies a significant percentage of the silicon area in a microprocessor due its wide data bandwidth (for double-precision computations) and the area occupied by the multiply array. For microprocessors designed for portable products, the design-size of the floating-point unit plays an important role in the low cost factor driven by reduced chip area. Some microprocessors have multiply-add fused floating-point units with a reduced multiply array, requiring two passes through the array for operations involving double-precision multiplies. This paper discusses the design complexities around the dual-pass multiply array and its effect on area and performance. Floating-point unit areas and their associated multiply array areas are compared for a single- and dual-pass implementation in a given technology (PowerPC 604eTM and PowerPC 603eTM microprocessors, respectively).

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Index Terms:
Floating-point unit, multiply-add fused, multiply array, alignment shifter, sign encoding, Booth encoding.
Citation:
Romesh M. Jessani, Michael Putrino, "Comparison of Single- and Dual-Pass Multiply-Add Fused Floating-Point Units," IEEE Transactions on Computers, vol. 47, no. 9, pp. 927-937, Sept. 1998, doi:10.1109/12.713312
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