This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Deriving Logic Systems for Path Delay Test Generation
August 1998 (vol. 47 no. 8)
pp. 829-846

Abstract—We present an algorithm to derive logic systems for various classes of path delay test problems. In these logic systems, the value of a signal represents the relevant conditions that occur during a set of consecutively applied vectors. Starting from a set of basic values for valid signals at primary inputs, a state transition graph is constructed to enumerate all possible signal states relevant to path activation that are reachable by Boolean operations. These states include all incompletely specified states, composed as combinations of basic values. A distinguishability analysis then finds all state-pairs that need to be distinguished during test generation. The final step minimizes the number of states. For forward and backward implications of test generation in combinational or sequential circuits, the procedure provides optimal logic systems. We define optimality as the smallest set of logic states that provides the least possible ambiguity in implications. Thus, an optimal set of logic states will minimize the number of backtracks in test generation. A 10-valued logic described in the literature is found to be optimal for generating tests for single path delay faults. Other problems addressed in this paper include compact test generation through activation of many single path delay faults, test generation for rated-clock test application, and test generation for multiple path delay faults. The limitations and capabilities of various logic systems are illustrated by examples.

[1] J.P. Hayes, "Uncertainty, Energy, and Multiple-Valued Logics," IEEE Trans. Computers, vol. 35, no. 2, pp. 107-114, Feb. 1986.
[2] J.T. Butler, "Multiple-Valued Logic: Lifting the Two-Lane Restriction," Computer, vol. 21, no. 4, Apr. 1986.
[3] J.P. Roth, "Diagnosis of Automata Failures: A Calculus and a Method," IIBM Technical J., vol. 10, pp. 278-291, July 1966.
[4] S. Bose, P. Agrawal, and V.D. Agrawal, "Logic Systems for Path Delay Test Generation," Proc. EURO-DAC, pp. 200-205, Sept. 1993.
[5] J. Rajski and H. Cox, "A Method of Test Generation and Fault Diagnosis in Very Large Combinational Circuits," Proc. Int'l Test Conf., pp. 932-943, Sept. 1987.
[6] W. Kunz and D. Stoffel, Reasoning in Boolean Networks.Boston: Kluwer Academic, 1997.
[7] S.T. Chakradhar, V.D. Agrawal, and S.G. Rothweiler, "A Transitive Closure Algorithm for Test Generation," IEEE Trans. Computer-Aided Design, vol. 12, pp. 1,015-1,028, July 1993.
[8] K. Fuchs, F. Fink, and M.H. Schulz, "DYNAMITE: An Efficient Automatic Test Pattern Generation System for Path Delay Faults," IEEE Trans. Computer-Aided Design, vol. 10, pp. 1,323-1,335, Oct. 1991.
[9] M.H. Schulz, K. Fuchs, and F. Fink, "Advanced Automatic Test Pattern Generation Techniques for Path Delay Faults," Proc. 19th Fault Tolerant Computing Symp., pp. 44-51, June 1989.
[10] C.J. Lin and S.M. Reddy, "On Delay Fault Testing in Logic Circuits," Proc. Int'l Conf. Computer Aided Design, pp. 148-151, Nov. 1986.
[11] M.A. Gharaybeh, M.L. Bushnell, and V.D. Agrawal, "Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests," J. Electronic Testing: Theory and Applications, vol. 11, pp. 55-67, Aug. 1997.
[12] G.L. Smith, "Model for Delay Faults Based upon Paths," Proc. Int'l Test Conf., pp. 342-349, Sept. 1985.
[13] J.E. Hopcroft and J.D. Ullman, Introduction to Automata Theory, Languages and Computation. Addison-Wesley, Apr. 1979.
[14] C.J. Lin and S.M. Reddy, "On Delay Testing in Logic Circuits," IEEE Trans. Computer-Aided Design, vol. 6, pp. 694-701, Sept. 1987.
[15] A.V. Aho, J.E. Hopcroft, and J.D. Ullman, The Design and Analysis of Computer Algorithms, pp. 158-162.Reading, Mass.: Addison-Wesley, 1974.
[16] S. Bose, P. Agrawal, and V.D. Agrawal, "Generation of Compact Delay Tests by Multiple Path Activation," Proc. Int'l Test Conf., pp. 714-723, Oct. 1993.
[17] S. Bose, P. Agrawal, and V.D. Agrawal, "Path Delay Fault Simulation of Sequential Circuits," IEEE Trans. VLSI Systems, vol. 1, pp. 453-461, Dec. 1993.
[18] K. Fuchs, M. Pabst, and T. Rossel, "RESIST: A Recursive Test Pattern Generation Algorithm for Path Delay Faults Considering Various Test Classes," IEEE Trans. Computer Aided Design, vol. 13, pp. 1,550-1,562, Nov. 1994.
[19] K. Fuchs, H.C. Wittmann, and K.J. Antreich, "Fast Test Pattern Generation for All Path Delay Faults Considering Various Test Classes," Proc. European Test Conf., pp. 89-98, Apr. 1993.
[20] T.J. Chakraborty, V.D. Agrawal, and M.L. Bushnell, "Delay Fault Models and Test Generation for Random Logic Sequential Circuits," Proc. 29th Design Automation Conf., pp. 165-172, June 1992.
[21] T.J. Chakraborty, V.D. Agrawal, and M.L. Bushnell, "Path Delay Fault Simulation Algorithms for Sequential Circuits," Proc. First Asian Test Symp., pp. 52-56, Nov. 1992.
[22] T.J. Chakraborty, V.D. Agrawal, and M.L. Bushnell, "On Variable Clock Methods for Path Delay Testing of Sequential Circuits," IEEE Trans. Computer-Aided Design, vol. 16, pp. 1,237-1,249, Nov. 1997.
[23] Y.C. Hsu and S.K. Gupta, "A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits," IEEE Trans. Computers, vol. 45, pp. 1,312-1,318, Nov. 1996.
[24] S. Bose, "Testing for Path Delay Faults in Synchronous Digital Circuits," PhD thesis, Carnegie Mellon Univ., Pittsburgh, Penn., Dec. 1995.
[25] S. Bose, P. Agrawal, and V.D. Agrawal, "A Rated-Clock Test Method for Path Delay Faults," IEEE Trans. VLSI Systems, vol. 6, pp. 323-331, June 1998.
[26] W. Ke and P.R. Menon, "Synthesis of Delay-Verifiable Combinational Circuits," IEEE Trans. Computers, vol. 44, pp. 213-222, Feb. 1995.
[27] A. Krstic and K.T. Cheng, "Generation of High Quality Tests for Functionally Sensitizable Paths," Proc. 13th VLSI Test Symp., pp. 374-379, May 1995.
[28] S. Bose, P. Agrawal, and V.D. Agrawal, "The Optimistic Update Theorem for Path Delay Fault Testing," J. Electronic Testing: Theory and Applications, vol. 4, pp. 285-290, Aug. 1993.
[29] K. Heragu, "New Techniques to Verify Timing Correctness of Integrated Circuits," PhD thesis, Univ. Illi nois, Urbana-Champaign, 1998.
[30] M.H. Schulz and E. Auth, "Improved Deterministic Test Pattern Generation with Applications to Redundancy Identification," IEEE Trans. Computer-Aided Design, vol. 8, pp. 811-817, July 1989.
[31] M.H. Schulz, E. Trischler, and T.M. Safert, "Socrates: A Highly Efficient Automatic Test Pattern Generation Systen," IEEE Trans. Computer-Aided Design, vol. 7, pp. 126-137, Jan. 1988.
[32] K.T. Cheng and H. Chen, "Delay Testing for Nonrobust Untestable Circuits," Proc. Int'l Test Conf., pp. 954-961, Oct. 1993.

Index Terms:
Delay testing, digital test, multivalued logic, path delay faults, simulation, timing analysis.
Citation:
Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal, "Deriving Logic Systems for Path Delay Test Generation," IEEE Transactions on Computers, vol. 47, no. 8, pp. 829-846, Aug. 1998, doi:10.1109/12.707585
Usage of this product signifies your acceptance of the Terms of Use.