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Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal, "Deriving Logic Systems for Path Delay Test Generation," IEEE Transactions on Computers, vol. 47, no. 8, pp. 829846, August, 1998.  
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@article{ 10.1109/12.707585, author = {Soumitra Bose and Prathima Agrawal and Vishwani D. Agrawal}, title = {Deriving Logic Systems for Path Delay Test Generation}, journal ={IEEE Transactions on Computers}, volume = {47}, number = {8}, issn = {00189340}, year = {1998}, pages = {829846}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.707585}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  Deriving Logic Systems for Path Delay Test Generation IS  8 SN  00189340 SP829 EP846 EPD  829846 A1  Soumitra Bose, A1  Prathima Agrawal, A1  Vishwani D. Agrawal, PY  1998 KW  Delay testing KW  digital test KW  multivalued logic KW  path delay faults KW  simulation KW  timing analysis. VL  47 JA  IEEE Transactions on Computers ER   
Abstract—We present an algorithm to derive logic systems for various classes of path delay test problems. In these logic systems, the value of a signal represents the relevant conditions that occur during a set of consecutively applied vectors. Starting from a set of basic values for valid signals at primary inputs, a state transition graph is constructed to enumerate all possible signal states relevant to path activation that are reachable by Boolean operations. These states include all incompletely specified states, composed as combinations of basic values. A distinguishability analysis then finds all statepairs that need to be distinguished during test generation. The final step minimizes the number of states. For forward and backward implications of test generation in combinational or sequential circuits, the procedure provides optimal logic systems. We define optimality as the smallest set of logic states that provides the least possible ambiguity in implications. Thus, an optimal set of logic states will minimize the number of backtracks in test generation. A 10valued logic described in the literature is found to be optimal for generating tests for single path delay faults. Other problems addressed in this paper include compact test generation through activation of many single path delay faults, test generation for ratedclock test application, and test generation for multiple path delay faults. The limitations and capabilities of various logic systems are illustrated by examples.
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