This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Long and Fast Up/Down Counters
July 1998 (vol. 47 no. 7)
pp. 722-735

Abstract—This paper presents recent advances in the design of constant-time up/down counters in the general context of fast counter design. An overview of existing techniques for the design of long and fast counters reveals several methods closely related to the design of fast adders, as well as some techniques that are only valid for counter design. The main idea behind the novel up/down counters is to recognize that the only extra difficulty with an up/down (vs. up-only or down-only) counter is when the counter changes direction from counting up to counting down (and vice-versa). For dealing with this difficulty, the new design uses a "shadow" register for storing the previous counter state. When counting only up or only down, the counter functions like a standard up-only or down-only constant time counter, but, when it changes direction instead of trying to compute the new value (which typically requires carry propagation), it simply uses the contents of the shadow register which contains the exact desired previous value. An alternative approach for restoring the previous state in constant time is to store the carry bits in a Carry/Borrow register.

[1] S. Amuro, "Adjacent Code System," U.S. Patent no. 5,329,280, July 1994.
[2] D. Chu and M. Ward, "Data Capture in an Uninterrupted Counter," U.S. Patent no. 4,519,091, May 1985.
[3] D.H. Eby, "Synchronous Programmable Two-Stage Serial/Parallel Counter," U.S. Patent no. 4,905,262, Feb. 1990.
[4] M.D. Ercegovac and T. Lang, "Binary Counter with Counting Period of One Half Adder Independent of Counter Size," IEEE Trans. Circuits and Systems, vol. 36, pp. 924-926, June 1989.
[5] M.W. Evans, "Minimal Logic Synchronous Up/Down Counter Implemenations for CMOS," U.S. Patent no. 4,611,337, Sept. 1986.
[6] D.C. Hendry, "Sequential Lookahead Method for Digital Counters," Electronics Letters, vol. 32, pp. 160-161, Feb. 1996.
[7] T. Iida and T. Ikarashi, "Synchronous Binary Counter," U.S. Patent no. 4,679,216, July 1987.
[8] J. Kalisz, R. Szplet, R. Pelka, and A. Poniecki, "Single-Chip Interpolating Time Counter with 200-ps Resolution and 43-s Range," IEEE Trans. Instrumentation and Measurement, vol. 46, pp. 851-856, Aug. 1997.
[9] M. Katoozi and M. Soma, "A Testable CMOS Synchronous Counter," IEEE J. Solid-State Circuits, vol. 23, pp. 1,241-1,248, Oct. 1988.
[10] M. Kondo and T. Watnabe, "Synchronous Counter," U.S. Patent no. 5,526,393, June 1996.
[11] I. Koren, Computer Arithmetic Algorithms.Englewood Cliffs, N.J.: Prentice Hall, 1993.
[12] P. Larsson and J.R. Yuan, "Novel Carry Propagation in High-Speed Synchronous Counters and Dividers," Electronics Letters, vol. 29, pp. 1,457-1,458, Aug. 1993.
[13] S.-K. Lee, "Binary Counter with Sped-Up Ripple Carry," U.S. Patent no. 5,559,844, Sept. 1996.
[14] D.R. Lutz and D.N. Jaysimha, "Programmable Modulo-k Counter," IEEE Trans. Circuits and Systems, vol. 43, pp. 939-941, Nov. 1996.
[15] B. Norris, Digital Integrated Circuits and Operational-Amplifier and Optoelectronic Circuit Design.New York: McGraw-Hill, 1976.
[16] K.Z. Pekmestzi and N. Thanasouras, "Systolic Frequency-Dividers Counters," IEEE Trans. Circuits and Systems, vol. 41, pp. 775-776, Nov. 1994.
[17] W.W. Person, Error Correcting Codes.Cambridge, Mass.: MIT Press, 1961.
[18] J.M. Rabaey, Digital Integrated CircuitsUpper Saddle River, N.J.: Prentice Hall, 1996.
[19] S.R. Ramirez, "Counter Cell and Counter Circuit," U.S. Patent no. 5,495,513, Feb. 1996.
[20] R. Rogenmoser, Q. Huang, and F. Piazza, "1.57 GHz Asynchronous and 1.4 GHz Dual-Modulus 1.2 mm CMOS Prescalers," Proc. Custom Integrated Circuits Conf., pp. 387-390, May 1994.
[21] M.R. Stan, "Shift-Register Generators for Circular FIFOs," Electronic Eng., pp. 26-27, Feb. 1991.
[22] M.R. Stan, "Synchronous Up/Down Counter with Period Independent of Counter Size," Proc. IEEE Symp. Computer Arithmetic, pp. 274-281,Asilomar, Calif., July 1997.
[23] A.F. Tenca and M.D. Ercegovac, "Synchronous Up/Down Binary Counter for LUT FPGAs with Counting Frequency Independent of Counter Size," Proc. Int'l Symp. FPGAs, pp. 159-165,Monterey, Calif., Feb. 1997.
[24] J.D. Ullman, Computational Aspects of VLSI.Rockville, Md.: Computer Science Press, 1984.
[25] N.J. Higham, "Iterative Refinement Enhances the Stability of QR Factorization Methods for Solving Liner Equations," BIT, vol. 31, pp. 447-468, 1991.
[26] K. Windmiller, "Integrated High Speed Synchronous Counter with Asynchronous Read-Out," U.S. Patent no. 5,045,854, Sept. 1991.
[27] Xilinx, The Programmable Logic Data Book. Aug. 1993.
[28] G. Yasar, Y. Tsyrkina, and D. Thygesen, "Fpga Fast Counter Design," Proc. Canadian Workshop FPDs, pp. 37-43, Toronto, Canada, May 1996.
[29] J.R. Yuan, "Efficient CMOS Counter Circuits," Electronics Letters, vol. 24, pp. 1,311-1,313, Oct. 1988.
[30] J.R. Yuan and C. Svensson, "Fast CMOS Nonbinary Divider and Counter," Electronics Letters, vol. 29, pp. 1,222-1,223, June 1993.
[31] Z. Zilic, G. Lemieux, K.L.S. Brown, and Z. Vranesic, "Designing for High Speed-Performance in cplds and fpgas," Proc. Canadian Workshop FPDs,Montreal, Canada, May 1995.

Index Terms:
Binary counter, constant time counter, serial counter, parallel counter, prescaler, up/down counter.
Citation:
Mircea R. Stan, Alexandre F. Tenca, Milos D. Ercegovac, "Long and Fast Up/Down Counters," IEEE Transactions on Computers, vol. 47, no. 7, pp. 722-735, July 1998, doi:10.1109/12.709372
Usage of this product signifies your acceptance of the Terms of Use.