This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Combining Trace Sampling with Single Pass Methods for Efficient Cache Simulation
June 1998 (vol. 47 no. 6)
pp. 714-720

Abstract—The design of the memory hierarchy is crucial to the performance of high performance computer systems. The incorporation of multiple levels of caches into the memory hierarchy is known to increase the performance of high end machines, but the development of architectural prototypes of various memory hierarchy designs is costly and time consuming. In this paper, we will describe a single pass method used in combination with trace sampling techniques to produce a fast and accurate approach for simulating multiple sizes of caches simultaneously.

[1] R.L. Mattson, J. Gercsei, D.R. Slutz, and I.L. Traiger, "Evaluation Techniques for Storage Hierarchies," IBM Systems J., vol. 9, no. 2, pp. 78-117, 1970.
[2] A. Agarwal, M. Horowitz, and J. Hennessy, "An Analytical Cache Model," ACM Trans. Computer Systems, vol. 7, pp. 184-215, May 1989.
[3] A.J. Smith, "A Second Bibliography on Cache Memories," Computer Architecture News, vol. 19, pp. 138-153, June 1991.
[4] I.L. Traiger and D.R. Slutz, "One-Pass Techniques for the Evaluation of Memory Hierarchies," IBM Research Report RJ 892, IBM, San Jose, Calif., July 1971.
[5] J.G. Thompson and A.J. Smith, "Efficient (Stack) Algorithms for Analysis of Write-Back and Sector Memories," ACM Trans. Computer Systems, vol. 7, pp. 78-117, Feb. 1989.
[6] M. Hill and A. Smith, "Evaluating Associativity in CPU Caches," IEEE Trans. Computers, vol. 38, no. 12, pp. 1,612-1,630, Dec. 1989.
[7] R.E. Kessler, M.D. Hill, and D.A. Wood, "A Comparison of Trace-Sampling Techniques for Multi-Megabyte Caches," IEEE Trans. Computers, vol. 43, no. 6, pp. 664-675, June 1994.
[8] S. Laha, J.A. Patel, and R.K. Iyer, "Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems," IEEE Trans. Computing, Feb. 1988, pp. 1,325-1,336.
[9] H.S. Stone, High-Performance Computer Architecture.Reading, Mass.: Addison-Wesley, 1990.
[10] K.R. Kaplan and R.O. Winder, "Cache-Based Computer Systems," Computer, vol. 6, pp. 30-36, Mar. 1973.
[11] W.W. Hwu and T.M. Conte, "A Simulation Study of Simultaneous Vector Prefetch Performance in Multiprocessor Memory Subsystems," Proc. ACM SIGMETRICS '89 Conf. Measurement and Modeling of Computer Systems, p. 227,Berkeley, Calif., May 1989.
[12] A.J. Smith, "Cache Memories," ACM Computing Surveys, Vol. 14, 1982, pp. 473-540.
[13] T.M. Conte and W.W. Hwu, "Benchmark Characterization," Computer, pp. 48-56, Jan. 1991.
[14] J.W.C. Fu and J.H. Patel, "How to Simulate 100 Billion References Cheaply," Technical Report CRHC-91-30, Center for Reliable and High-Performance Computing, Univ. of Illinois at Urbana-Champaign, Urbana, Ill., Nov. 1991.
[15] W.W. Hwu and T.M. Conte, "The Susceptibility of Programs to Context Switching," IEEE Trans. Computers, vol. 43, no. 9, pp. 993-1,003, Sept. 1994.

Index Terms:
Performance analysis, sampling techniques, single pass algorithms, stacking algorithms, trace-driven simulation.
Citation:
Thomas M. Conte, Mary Ann Hirsch, Wen-Mei W. Hwu, "Combining Trace Sampling with Single Pass Methods for Efficient Cache Simulation," IEEE Transactions on Computers, vol. 47, no. 6, pp. 714-720, June 1998, doi:10.1109/12.689650
Usage of this product signifies your acceptance of the Terms of Use.