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| Eskil Dekker, "Architecture Scalability of Parallel Vector Computers with a Shared Memory," IEEE Transactions on Computers, vol. 47, no. 5, pp. 614-624, May, 1998. | |||
| BibTex | x | ||
| @article{ 10.1109/12.677257, author = {Eskil Dekker}, title = {Architecture Scalability of Parallel Vector Computers with a Shared Memory}, journal ={IEEE Transactions on Computers}, volume = {47}, number = {5}, issn = {0018-9340}, year = {1998}, pages = {614-624}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.677257}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Architecture Scalability of Parallel Vector Computers with a Shared Memory IS - 5 SN - 0018-9340 SP614 EP624 EPD - 614-624 A1 - Eskil Dekker, PY - 1998 KW - Architecture scalability KW - parallel vector computers KW - shared memory KW - sustainable peak performance KW - theoretical peak performance. VL - 47 JA - IEEE Transactions on Computers ER - | |||
Abstract—Based on a model of a parallel vector computer with a shared memory, its scalability properties are derived. The processor-memory interconnection network is assumed to be composed of crossbar switches of size
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