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Logic Testing of Bridging Faults in CMOS Integrated Circuits
March 1998 (vol. 47 no. 3)
pp. 338-345

Abstract—We describe a system for simulating and generating accurate tests for bridging faults in CMOS ICs. After introducing the Primitive Bridge Function, a characteristic function describing the behavior of a bridging fault, we present the Test Guarantee Theorem, which allows for accurate test generation for feedback bridging faults via topological analysis of the feedback-influenced region of the faulty circuit. We present a bridging fault simulation strategy superior to previously published strategies, describe the new test pattern generation system in detail, and report on the system's performance, which is comparable to that of a single stuck-at ATPG system. The paper reports fault coverage as well as defect coverage for the MCNC layouts of the ISCAS-85 benchmark circuits.

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Index Terms:
Bridging faults, fault simulation, test pattern generation, realistic faults, fault models.
Citation:
Brian Chess, Tracy Larrabee, "Logic Testing of Bridging Faults in CMOS Integrated Circuits," IEEE Transactions on Computers, vol. 47, no. 3, pp. 338-345, March 1998, doi:10.1109/12.660170
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