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A Simplified Architecture for Modulo (2n + 1) Multiplication
March 1998 (vol. 47 no. 3)
pp. 333-337

Abstract—The modulo (2n + 1) multiplication is widely used in the computation of convolutions and in RNS arithmetic and, thus, it is important to reduce the calculation delay. This paper presents a concept of a modulo (2n + 1) carry save adder (MCSA) and uses two MCSAs to perform the residue reduction. We also apply Booth's algorithm to the modulo (2n + 1) multiplication scheme in order to reduce the number of partial products. With these techniques, the new architecture reduces the multiplier's calculation delay and is suitable for VLSI implementation for moderate and large n (n≥ 16).

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Index Terms:
Convolution, Fermat number transform, RNS arithmetic, modulo (2n + 1) multiplication, Booth's algorithm, Wallace tree, carry save adder, CSA array, carry lookahead adder.
Yutai Ma, "A Simplified Architecture for Modulo (2n + 1) Multiplication," IEEE Transactions on Computers, vol. 47, no. 3, pp. 333-337, March 1998, doi:10.1109/12.660169
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