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A Simplified Architecture for Modulo (2n + 1) Multiplication
March 1998 (vol. 47 no. 3)
pp. 333-337

Abstract—The modulo (2n + 1) multiplication is widely used in the computation of convolutions and in RNS arithmetic and, thus, it is important to reduce the calculation delay. This paper presents a concept of a modulo (2n + 1) carry save adder (MCSA) and uses two MCSAs to perform the residue reduction. We also apply Booth's algorithm to the modulo (2n + 1) multiplication scheme in order to reduce the number of partial products. With these techniques, the new architecture reduces the multiplier's calculation delay and is suitable for VLSI implementation for moderate and large n (n≥ 16).

[1] C. Fernstrom, I. Kruzela, and B. Svensson, LUCAS Associative Array Processor: Design, Programming and Application Studies, Lecture Notes in Computing Science, no. 216, Springer-Verlag, New York, 1986.
[2] W.D. Hillis, The Connection Machine, MIT Press, Cambridge, Mass., 1985.
[3] A.D. Booth, "A Signed Binary Multiplication Technique," Quarterly J. Mechanical Applications of Math., vol. 4, pt. 2, pp. 236-240, 1951.
[4] R.P. Brent and H.T. Kung, "A Regular Layout for Parallel Adders," IEEE Trans. Computers, vol. 31, no. 3, pp. 260-264, Mar. 1982.
[5] J.J. Chang, T.K. Truong, H.M. Shao, I.S. Reed, and I.S. Hsu, "The VLSI Design of a Single Chip for the Multiplication of Integers Modulo a Fermat Number," IEEE Trans. Acoustics Speech and Signal Processing., vol. 33, no. 6, pp. 1,599-1,602, Dec. 1985.
[6] A.V. Curiger, H. Bonnenberg, and H. Kaeslin, "Regular VLSI Architectures for Multiplication Modulo (2n+ 1)," IEEE J. Solid-State Circuits, vol. 26, no. 7, pp. 990-994, July 1991.
[7] C. Efstathiou, D. Nikolos, and J. Kalamatianos, Area-Time Efficient Modulo$2^n-1$Adder Design IEEE Trans. Circuits and Systems II, vol. 41, no. 7, pp. 463-467, 1994.
[8] L.M. Leibowitz, A Simplified Binary Arithmetic for the Fermat Number Transform IEEE Trans. Acoustics, Speech, Signal Processing, vol. 24, pp. 356-359, 1976.
[9] T.F. Ngai, M.J. Irwin, S. Rawat, "Regular, Area-Time Efficient Carry Lookahead Adders," J. Parallel and Distributed Computing, vol. 3, no. 1, pp. 92-105, Mar. 1986.
[10] D. Radhakrishnan and Y. Yuan, “Novel Approaches to the Design of VLSI RNS Multipliers,” IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 39, pp. 52-57, Jan. 1992.
[11] F.J. Taylor, "A VLSI Residue Arithmetic Multiplier," IEEE Trans. Computers, vol. 31, no. 6, pp. 540-546, June 1982.
[12] F. Taylor, A Single Modulus ALU for Signal Processing IEEE Trans. Acoustics, Speech, Signal Processing, vol. 33, pp. 1302-1315, 1985.
[13] P.J. Towers, A. Pajayakrit, and A.G.J. Holt, "Cascadable NMOS VLSI Circuit for Implementing a Fast Convolver Using the Fermat Number Transform," IEE Proc. G, vol. 134, no. 2, pp. 57-66, 1987.
[14] T.K. Truong, I.S. Reed, C.S. Yeh, and H.M. Shao, "A Parallel VLSI Architecture for a Digital Filter of Arbitrary Length Using Fermat Number Transforms," Proc. IEEE Int'l Conf. Circuits and Computers, pp. 574-576, 1982.
[15] C.S. Wallace, "A Suggestion for a Fast Multiplier," IEEE Trans. Electronic Computers, vol. 13, pp. 14-17, Feb. 1964.
[16] A. Wrzyszcz and D. Milford, "A New Modulo 2a+ 1 Multiplier," Proc. IEEE Int'l Conf. Computer Design, pp. 614-617,Cambridge, Mass., Oct.3-6, 1993.

Index Terms:
Convolution, Fermat number transform, RNS arithmetic, modulo (2n + 1) multiplication, Booth's algorithm, Wallace tree, carry save adder, CSA array, carry lookahead adder.
Citation:
Yutai Ma, "A Simplified Architecture for Modulo (2n + 1) Multiplication," IEEE Transactions on Computers, vol. 47, no. 3, pp. 333-337, March 1998, doi:10.1109/12.660169
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